sid-20110801 Patch to fix multiple cache line aging
Currently the SID cache component references the same lru_replacement
object each time it creates a lru cache. This causes configurations
with multiple caches (e.g. an Icache and Dcache) to use the same lru
array to track the line ages which creates problems since the array
no longer reflects the age of the lines in either cache. Each cache
needs their own (private) lru array.
Based on code inspection it appears fifo_replacement suffers the same
The enclosed patch has been tested on FreeBSD with sid configured for
tomi Borealis (a processor under development by Venray Technology).