Currently when the SID cache component replaces a line which is dirty
it writes back the data to memory. However it ignores that fact that
the writeback adds to the latency causing the simulation to believe
that the replacement of a dirty cache line takes the same amount of
time as the replacement of a clean cache line.
The enclosed patch has been tested on FreeBSD with sid configured for
tomi Borealis (a processor under development by Venray Technology).