[patch][rfc] sh64: Add Pipeline Modelling and SID Support

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[patch][rfc] sh64: Add Pipeline Modelling and SID Support

Dave Brolley-2
I would like to commit this patch which does the following for the sh64
target:

1) Add support for generating a SID simulator.
2) Add pipeline modelling for all sh machines (currently used only by SID).
3) Adds support for some previously unsupported insns (both SID and
sim/sh64).

I will submit the changes needed for sim/sh64 and sid separately. The
sim/sh simulator is currently not generated by CGEN.

NOTES:
o This is a patch against the existing sh.cpu, sh64-compact.cpu and
sh64-media.cpu in the cgen/cpu directory and which are currently used to
generate the sh64 simulator in sim/sh64. .cpu files also exist in the  
cpu directory, but they appear to be out of date compared to the ones in
cgen/cpu. Any clarification regarding which files are being actively
maintained would be much appreciated!

o The new files sh-sid.cpu and sh-sim.cpu provide pmacros for handling
the differences between generating sid and sim.

Comments, concerns and, ultimately, approval to commit please!

Thanks,
Dave

2006-08-22  Dave Brolley  <[hidden email]>

        * Contribute the following changes which add sid support as well as
        pipeline modeling for all sh machines (used by sid). In addition, some
        previously unsupported insns are now supported by both sim and sid.

        2006-07-11  Dave Brolley  <[hidden email]>

        * cpu/sh64-compact.cpu (movual, movual2): New insns.
        (movcol): New insn.
        * cpu/sh.cpu (sh4a-nofpu-models): New pmacro.
        * sid.scm (-op-gen-delayed-set-maybe-trace): If delay used, note the
        hardware or memory mode which was used.
        * sid-cpu.scm (hw-need-write-stack?): New function.
        (-gen-hw-stream-and-destream-fns): Compute stack-regs. Use it to
        identify hardware which uses write stacks.
        (useful-mode-names): Renamed to write-stack-memory-mode-names.
        Initialized to an empty list.
        (-gen-writestacks, -gen-reset-fn, -gen-unified-write-fn): Use
        hw-need-write-stack?.
        * hardware.scm (used-in-delay-rtl?): New member of <hardware-base>.
        (define-getters <hardware-base>): Define used-in-delay-rtl?.
        (used-in-delay-rtl?): New method of <hardware-base>.
        (hw-used-in-delay-rtl?): New function.

        2006-06-20  Dave Brolley  <[hidden email]>

        * sid.scm (gen-attr-type): Removed.
        * cpu/sh.cpu (SH2a-nofpu-MACH): Add sh5.
        (SH2a-MACH): Add sh5.
        (sh2a-nofpu-models): Add units for sh5.
        (sh2a-fpu-models): Likewise.

        2006-06-15  Dave Brolley  <[hidden email]>

        * cpu/sh-sim.cpu: New file.
        * cpu/sh-sid.cpu: New file.
        * cpu/sh64-media.cpu (dshci): Add xtiming argument and splice it in.
        (All fields): Remap for (insn-lsb0? #f)
        (All insns): Add timing specs.
        * cpu/sh64-compact.cpu (dshcf,dshcop): Replace 'ignored' argument with
        'xattrs' and .splice it in.
        (32-BIT-INSN,SH4-GROUP,SH4A-GROUP): New insn attributes.
        (h-frc,h-drc): Add PROFILE attribute.
        (h-fpccr): Removed.
        (h-vbr): New hardware.
        (All fields): Remap for (insn-lsb0? #f)
        (f-imm20-hi,f-imm20-lo,f-imm20): New fields.
        (fr0,fmovm,fmovn,imm20,imm12x4,imm12x8,vbr): New operands.
        (fpscr): Use h-fpscr.
        (fsdm,fsdn): Use h-fsd.
        (dshci): Add xtiming argument and splice it in.
        (dr,xd): pmacros removed.
        (All insns): Add timing specs, *-MACH attribibutes,
        SH4{A}-GROUP attributes.
        (divu,mulr,ldc-vbr,ldc-sr,ldcl-vbr,movl12,movl13,stcl-vbr): New insns.
        * cpu/sh.cpu): Include sh-sid.cpu or sh-sim.cpu depending on whether
        we're being processed for sim or sid.
        (define-arch): Change insn-lsb0? for #f. Add machs sh2e, sh2a-fpu,
        sh2a-nofpu, sh4-nofpu, sh4a-nofpu, sh4a, sh4al.
        (define-isa compact): Add (isa-parallel-insns 2).
        (define-isa media): Add (isa-parallel-insns 2). Add
        (default-insn-word-bitsize 32). Change base-insn-bitsize to 32.
        (define-mach): Add sh2e, sh2a-fpu, sh2a-nofpu, sh4-nofpu, sh4a-nofpu,
        sh4a, sh4al
        (SH2-MACH, SH2e-MACH, SH2a-nofpu-MACH, SH2a-MACH, SH3-MACH)
        (SH3e-MACH, SH4-nofpu-MACH, SH4-MACH, SH4a-nofpu-MACH, SH4a-MACH)
        (SH4al-MACH, SH5-MACH): New pmacros.
        (common-units, common-fp-units, sh2a-nofpu-units, sh2a-fpu-units)
        (sh4-nofpu-units, sh4-common-fp-units, sh5-media-units)
        (sh5-media-fp-units, common-model, common-model-with-fp)
        (sh3-model, sh3e-model): New pmacros.
        (define-model sh2): New model.
        (define-model sh2e): New model.
        (define-model sh3): New model.
        (define-model sh3e): New model.
        (define-model sh2a-nofpu): New model.
        (define-model sh2a-fpu): New model.
        (define-model sh4-nofpu): New model.
        (define-model sh4): New model.
        (define-model sh4a-nofpu): New model.
        (define-model sh4a): New model.
        (define-model sh4al): New model.
        (define-model sh5-media): New model.
        (define-model sh5): Add all units.
        (all-models, sh2e-models, sh2a-nofpu-models, sh2a-fpu-models)
        (sh3-models, sh3e-models, sh4-nofpu-models, sh4-models)
        (sh5-media-models, shad-models, fsqrt-models): New pmacros.
        (h-pc): Add PROFILE attribute.
        (h-fr): Likewise.
        (h-tr): Likewise.
        (h-gr,h-grc): Likewise.
        (h-cr): Set h-sr in setter.
        (h-frbit): Get/Set h-fpscr.
        (h-szbit,h-prbit): Likewise.
        (h-fp): Add PROFILE attribute. Now indexed by even indices 0-62.
        Add getter and setter.
        (h-fc): Add PROFILE attribute. Now indexed by quad indices 0-60.
        Adjust getter and setter.
        (h-fmtx): Add PROFILE attribute. Now indexed by 0, 16, 32 and 48.
        Adjust getter and setter.
        (h-dr): Add PROFILE attribute. Now indexed by even indices 0-62.
        (h-fsd,h-fmov): New hardware.


? cgen/cpu/sh-sid.cpu
? cgen/cpu/sh-sim.cpu
Index: cgen/cpu/sh.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/sh.cpu,v
retrieving revision 1.3
diff -c -p -r1.3 sh.cpu
*** cgen/cpu/sh.cpu 21 May 2003 14:10:46 -0000 1.3
--- cgen/cpu/sh.cpu 22 Aug 2006 17:22:26 -0000
***************
*** 1,15 ****
  ; Renesas / SuperH SH architecture description.  -*- Scheme -*-
! ; Copyright (C) 2000, 2001 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
  (include "simplify.inc")
 
  (define-arch
    (name sh)
    (comment "Renesas / SuperH SuperH (SH)")
!   (insn-lsb0? #t)
!   (machs sh2 sh3 sh3e sh4 sh5)
    (isas compact media)
  )
 
--- 1,25 ----
  ; Renesas / SuperH SH architecture description.  -*- Scheme -*-
! ; Copyright (C) 2000, 2001, 2006 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
  (include "simplify.inc")
 
+ ; Macros to handle differences in CGEN for SID vs SIM are included
+ ; here.
+ (if (application-is? SID-SIMULATOR)
+     (include "sh-sid.cpu")
+     (include "sh-sim.cpu"))
+
  (define-arch
    (name sh)
    (comment "Renesas / SuperH SuperH (SH)")
!   ; Should be #t but cgen can't handle variable length insns with #t
!   (insn-lsb0? #f)
!   (machs sh2 sh2e sh2a-fpu sh2a-nofpu
! sh3 sh3e
! sh4-nofpu sh4 sh4a-nofpu sh4a sh4al
! sh5)
    (isas compact media)
  )
 
***************
*** 20,31 ****
    (name media)
    (comment "SHmedia 32-bit instruction set")
    (base-insn-bitsize 32)
  )
 
  (define-isa
    (name compact)
!   (comment "SHcompact 16-bit instruction set")
!   (base-insn-bitsize 16)
  )
 
 
--- 30,46 ----
    (name media)
    (comment "SHmedia 32-bit instruction set")
    (base-insn-bitsize 32)
+   ; not really parallel but some operands are shared between
+   ; the ISAs and CGEN wants them all to be marked as parallel.
+   (isa-parallel-insns 2)
  )
 
  (define-isa
    (name compact)
!   (comment "SHcompact 16/32 bit instruction set")
!   (default-insn-word-bitsize 32)
!   (base-insn-bitsize 32)
!   (isa-parallel-insns 2)
  )
 
 
***************
*** 47,52 ****
--- 62,88 ----
  )
 
  (define-mach
+   (name sh2e)
+   (comment "SH-2e CPU core")
+   (cpu sh64)
+   (isas compact)
+ )
+
+ (define-mach
+   (name sh2a-fpu)
+   (comment "SH-2a CPU core with fpu")
+   (cpu sh64)
+   (isas compact)
+ )
+
+ (define-mach
+   (name sh2a-nofpu)
+   (comment "SH-2a CPU core with no fpu")
+   (cpu sh64)
+   (isas compact)
+ )
+
+ (define-mach
    (name sh3)
    (comment "SH-3 CPU core")
    (cpu sh64)
***************
*** 61,68 ****
  )
 
  (define-mach
    (name sh4)
!   (comment "SH-4 CPU core")
    (cpu sh64)
    (isas compact)
  )
--- 97,132 ----
  )
 
  (define-mach
+   (name sh4-nofpu)
+   (comment "SH-4 CPU core - no fpu")
+   (cpu sh64)
+   (isas compact)
+ )
+
+ (define-mach
    (name sh4)
!   (comment "SH-4 CPU core with fpu")
!   (cpu sh64)
!   (isas compact)
! )
!
! (define-mach
!   (name sh4a-nofpu)
!   (comment "SH-4a CPU core - no fpu")
!   (cpu sh64)
!   (isas compact)
! )
!
! (define-mach
!   (name sh4a)
!   (comment "SH-4a CPU core with fpu")
!   (cpu sh64)
!   (isas compact)
! )
!
! (define-mach
!   (name sh4al)
!   (comment "SH-4al CPU core")
    (cpu sh64)
    (isas compact)
  )
***************
*** 74,94 ****
    (isas compact media)
  )
 
! (define-model
    (name sh5)
!   (comment "SH-5 reference implementation")
    (mach sh5)
!   (unit u-exec "Execution unit" ()
! 1 1 ; issue done
! () () () ())
  )
 
  ; Hardware elements.
 
  (define-hardware
    (name h-pc)
    (comment "Program counter")
!   (attrs PC (ISA compact,media))
    (type pc UDI)
    (get () (raw-reg h-pc))
    (set (newval) (sequence ()
--- 138,1051 ----
    (isas compact media)
  )
 
! ; Partition insns according to the mach in which they first appear.
! (define-pmacro (SH2-MACH)        (MACH sh2,sh2e,sh2a-fpu,sh2a-nofpu,sh3,sh3e,sh4-nofpu,sh4,sh4a-nofpu,sh4a,sh4al,sh5)) ; sh2  and up
! (define-pmacro (SH2e-MACH)       (MACH sh2e,sh2a-fpu,sh3e,sh4,sh4a,sh5))                                               ; sh2e and up
! (define-pmacro (SH2a-nofpu-MACH) (MACH sh2a-nofpu,sh2a-fpu,sh4,sh4-nofpu,sh5))                                         ; sh2a and up
! (define-pmacro (SH2a-MACH)       (MACH sh2a-fpu,sh4,sh5))                                                                  ; sh2a with fpu and up
! (define-pmacro (SH3-MACH)        (MACH sh3,sh3e,sh4-nofpu,sh4,sh4a-nofpu,sh4a,sh4al,sh5))                              ; sh3  and up
! (define-pmacro (SH3e-MACH)       (MACH sh3e,sh4,sh4a,sh5))                                                             ; sh3e and up
! (define-pmacro (SH4-nofpu-MACH)  (MACH sh4-nofpu,sh4,sh4a-nofpu,sh4a,sh4al,sh5))                                       ; sh4 no fpu and up
! (define-pmacro (SH4-MACH)        (MACH sh4,sh4a,sh5))                                                                  ; sh4 and up
! (define-pmacro (SH4a-nofpu-MACH) (MACH sh4a-nofpu,sh4a,sh4al,sh5))                                                     ; sh4a no fpu and up
! (define-pmacro (SH4a-MACH)       (MACH sh4a,sh5))                                                                      ; sh4a with fpu and up
! (define-pmacro (SH4al-MACH)      (MACH sh4al))                                                                         ; sh4al and up
! (define-pmacro (SH5-MACH)        (MACH sh5))                                                                           ; sh5 compact and up
!
! ; Pipeline Models
!
! ; Units common to all machines
! (define-pmacro (common-units)
!   (
!    ; Basic execution unit -- 1 cycle
!    (unit u-exec "Execution unit" ()
! 1 1 ; issue done
! () () () ())
!
!    ; SX execution unit -- 1 cycle
!    ; Ignored on most machines
!    (unit u-sx "SX Execution unit" ()
! 1 1 ; issue done
! () () () ())
!
!    ; Branch unit
!    (unit u-branch "Branch Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((pc)) ; outputs
! () ; profile action (default)
! )
!
!    ; Jmp unit
!    (unit u-jmp "Jmp Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((pc)) ; outputs
! () ; profile action (default)
! )
!
!    ; JSR unit
!    (unit u-jsr "JSR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((pc)) ; outputs
! () ; profile action (default)
! )
!
!    ; Logic.b unit -- 3 cycles
!    (unit u-logic-b "Logic.b unit" ()
! 0 3 ; issue done
! () () () ())
!
!    ; Memory Access unit
!    (unit u-memory-access "Memory Access Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; LDS PR unit
!    (unit u-lds-pr "LDS PR Unit" ()
! 0 1 ; issue done
! () () () ())
!
!    ; STS PR unit
!    (unit u-sts-pr "STS PR Unit" ()
! 0 1 ; issue done
! () () () ())
!
!    ; Load PR unit
!    (unit u-load-pr "Load PR Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Use PR unit
!    (unit u-use-pr "Use PR Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Set SR Bit unit
!    (unit u-set-sr-bit "Set SR Bit Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; LDC SR unit
!    (unit u-ldc-sr "LDC SR Unit" ()
! 0 1 ; issue done
! () () () ())
!
!    ; LDC GBR unit
!    (unit u-ldc-gbr "LDC GBR Unit" ()
! 0 1 ; issue done
! () () () ())
!
!    ; Use TBIT unit
!    (unit u-use-tbit "Use TBIT Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; LDCL unit
!    (unit u-ldcl "LDCL Unit" ()
! 0 3 ; issue done
! () () () ())
!
!    ; LDCL to VBR unit
!    (unit u-ldcl-vbr "LDCL to VBR Unit" ()
! 0 3 ; issue done
! () () () ())
!
!    ; STC from VBR unit
!    (unit u-stc-vbr "STC from VBR Unit" ()
! 0 1 ; issue done
! () () () ())
!
!    ; Load gr unit
!    (unit u-load-gr "Load into GR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Use gr unit -- stalls if GR not ready
!    (unit u-use-gr "Use GR Unit" ()
! 0 0 ; issue done
! () ; state
! ((usereg INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!
!    ; Load GBR unit
!    (unit u-load-gbr "Load GBR Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Load VBR unit
!    (unit u-load-vbr "Load VBR Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Load MAC{H,L} unit
!    (unit u-load-mac "Load MAC Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Set MAC{H,L} Unit
!    (unit u-set-mac "Set MAC Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Multiply unit
!    (unit u-multiply "Multiply unit" ()
! 1 2 ; issue done
! () () () ())
!
!    ; mac.w Multiply unit
!    (unit u-macw "mac.w multiply unit" ()
! 1 2 ; issue done
! () () () ())
!
!    ; mac.l Multiply unit
!    (unit u-macl "mac.l multiply unit" ()
! 1 2 ; issue done
! () () () ())
!
!    ; dmul Multiply unit
!    (unit u-dmul "dmul{s,u},mull multiply unit" ()
! 1 2 ; issue done
! () () () ())
!
!    ; mull Multiply unit
!    (unit u-mull "mull multiply unit" ()
! 1 2 ; issue done
! () () () ())
!
!    ; muls.w Multiply unit
!    (unit u-mulsw "muls.w multiply unit" ()
! 1 1 ; issue done
! () () () ())
!
!    ; tas unit
!    (unit u-tas "tas unit" ()
! 1 4 ; issue done
! () () () ())
!
!    (unit u-shift "Shift Unit" ()
!   0 0 ; issue done
! () () () ())
!
!    ; Use multiply result unit -- stalls if multiply unit is busy
!    (unit u-use-multiply-result "Use Multiply Result Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Writeback unit
!    (unit u-write-back "Writeback Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Trap unit
!    (unit u-trap "Trap Unit" ()
! 0 8 ; issue done
! () () () ())
!   )
! )
!
! ; Units common to all floating point enabled machines
! (define-pmacro (common-fp-units)
!   (
!    ; Basic fpu unit -- 1 cycle
!    (unit u-fpu "FPU unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Maybe uses fpu -- must have same latency as u-fpu
!    (unit u-maybe-fpu "Maybe FPU unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Load fr unit
!    (unit u-load-fr "Load into FR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Set fr unit
!    (unit u-set-fr "Set FR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Set fr unit -- no latency on some machines
!    ; Define it with the same latency as u-set-fr
!    (unit u-set-fr-0 "Set FR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Use fr unit -- stalls if FR not ready
!    (unit u-use-fr "Use FR Unit" ()
! 0 0 ; issue done
! () ; state
! ((usereg INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!
!    ; FPU Memory Access unit
!    (unit u-fpu-memory-access "FPU Memory Access Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Set FPUL unit
!    (unit u-set-fpul "Set FPUL Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Load FPUL unit
!    (unit u-load-fpul "Load FPUL Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; FLDS FPUL unit
!    (unit u-flds-fpul "FLDS FPUL Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Use FPUL unit
!    (unit u-use-fpul "Use FPUL Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; LDS FPSCR unit
!    (unit u-lds-fpscr "LDS FPSCR Unit" ()
! 0 3 ; issue done
! () () () ())
!
!    ; LDS.L FPSCR unit
!    (unit u-ldsl-fpscr "LDS.L FPSCR Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; Use FPSCR unit
!    (unit u-use-fpscr "Use FPSCR Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; FPU Load gr unit
!    (unit u-fpu-load-gr "FPU Load into GR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; FDIV unit
!    (unit u-fdiv "FDIV Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; FSQRT unit -- not completely common but common enough
!    (unit u-fsqrt "FSQRT Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; FCMP unit
!    (unit u-fcmp "FCMP Unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; FCNV unit
!    (unit u-fcnv "FCNV Unit" ()
! 0 0 ; issue done
! () () () ())
!   )
! )
!
! ; Units common to sh2a-nofpu and above
! (define-pmacro (sh2a-nofpu-units)
!   (
!    ; mulr Multiply unit
!    (unit u-mulr "mulr multiply unit" ()
! 1 2 ; issue done
! () () () ())
!
!    ; mulr gr unit
!    (unit u-mulr-gr "MULR into GR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!   )
! )
!
! ; Units common to sh2a-fpu and above
! (define-pmacro (sh2a-fpu-units)
!   (
!    ; Set dr unit
!    (unit u-set-dr "Set DR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Load dr unit
!    (unit u-load-dr "Load into DR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Use dr unit -- stalls if DR not ready
!    (unit u-use-dr "Use DR Unit" ()
! 0 0 ; issue done
! () ; state
! ((usereg INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!   )
! )
!
! ; Units common to sh3 and above
! ;(define-pmacro (sh3-common-units)
! ;  (
! ;   (unit u-set-sr "Set SR Unit" ()
! ; 0 3 ; issue done
! ; () () () ())
! ;  )
! ;)
!
! ; Units common to sh4-nofpu and above
! (define-pmacro (sh4-nofpu-units)
!   (
!    ; OCB*  unit
!    (unit u-ocb "OCB* unit" ()
! 0 0 ; issue done
! () () () ())
!   )
! )
!
! ; Units common to sh4 and above with fp
! (define-pmacro (sh4-common-fp-units)
!   (
!    (unit u-fipr "FIPR Unit" ()
! 0 0 ; issue done
! () ; state
! ((fvm INT -1) (fvn INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!    (unit u-ftrv "FTRV Unit" ()
! 0 0 ; issue done
! () ; state
! ((fvn INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!   )
! )
!
! ; Units common to sh5 media and above
! (define-pmacro (sh5-media-units)
!   (
!    ; Load gr unit
!    (unit u-set-gr "Set into GR Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!   )
! )
!
! ; Units common to sh5 and above with fp
! (define-pmacro (sh5-media-fp-units)
!   (
!    ; Set fp unit
!    (unit u-set-fp "Set FP Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Set fv unit
!    (unit u-set-fv "Set FV Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Set mtrx unit
!    (unit u-set-mtrx "Set MTRX Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Load fp unit
!    (unit u-load-fp "Load FP Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Load fv unit
!    (unit u-load-fv "Load FV Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Load mtrx unit
!    (unit u-load-mtrx "Load MTRX Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; Use fp unit -- stalls if FP not ready
!    (unit u-use-fp "Use DR Unit" ()
! 0 0 ; issue done
! () ; state
! ((usereg INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!
!    ; Use fv unit -- stalls if FV not ready
!    (unit u-use-fv "Use DR Unit" ()
! 0 0 ; issue done
! () ; state
! ((usereg INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!
!    ; Use mtrx unit -- stalls if MTRX not ready
!    (unit u-use-mtrx "Use DR Unit" ()
! 0 0 ; issue done
! () ; state
! ((usereg INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!
!    ; Use TR unit -- stalls if TR not ready
!    (unit u-use-tr "Use TR Unit" ()
! 0 0 ; issue done
! () ; state
! ((usereg INT -1)) ; inputs
! () ; outputs
! () ; profile action (default)
! )
!
!    ; BLINK unit
!    (unit u-blink "BLINK Unit" ()
! 0 0 ; issue done
! () ; state
! ((targetreg INT -1)) ; inputs
! ((pc)) ; outputs
! () ; profile action (default)
! )
!
!    ; Conditional Branch unit
!    (unit u-cond-branch "Conditional branch Unit" ()
! 0 0 ; issue done
! () ; state
! ((targetreg INT -1)) ; inputs
! ((pc)) ; outputs
! () ; profile action (default)
! )
!
!    ; FDIV.D unit
!    (unit u-fdivd "FDIV.D Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; FSQRT.D unit
!    (unit u-fsqrtd "FSQRT.D Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; FTRV.S unit
!    (unit u-ftrvs "FTRVS Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((loadreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; PT* unit
!    (unit u-pt "PT* Unit" ()
! 0 0 ; issue done
! () ; state
! () ; inputs
! ((targetreg INT -1)) ; outputs
! () ; profile action (default)
! )
!
!    ; GETCFG unit
!    (unit u-getcfg "GETCFG unit" ()
! 0 0 ; issue done
! () () () ())
!
!    ; PUTCFG unit
!    (unit u-putcfg "PUTCFG unit" ()
! 0 0 ; issue done
! () () () ())
!   )
! )
!
! ; This macro is for all machines with identical timing
! (define-pmacro (common-model xmach)
!   (.splice define-model
!     (name xmach)
!     (comment (.str xmach " reference implementation"))
!     (mach xmach)
!     (.unsplice (common-units))
! ;    (unit u-set-sr "Set SR Unit" ()
! ;  0 1 ; issue done
! ;  () () () ())
!   )
! )
!
! ; This macro is for all fpu enabled machines with identical timing
! (define-pmacro (common-model-with-fp xmach)
!   (.splice define-model
!     (name xmach)
!     (comment (.str xmach " reference implementation"))
!     (mach xmach)
!     (.unsplice (common-units))
!     (.unsplice (common-fp-units))
! ;    (unit u-set-sr "Set SR Unit" ()
! ;  0 1 ; issue done
! ;  () () () ())
!   )
! )
!
! ; This macro is for all machines sh3 and up with identical timing
! (define-pmacro (sh3-model xmach)
!   (.splice define-model
!     (name xmach)
!     (comment (.str xmach " reference implementation"))
!     (mach xmach)
!     (.unsplice (common-units))
! ;    (.unsplice (sh3-common-units))
!   )
! )
!
! ; This macro is for all fpu enabled machines sh3e and up with identical timing
! (define-pmacro (sh3e-model xmach)
!   (.splice define-model
!     (name xmach)
!     (comment (.str xmach " reference implementation"))
!     (mach xmach)
!     (.unsplice (common-units))
!     (.unsplice (common-fp-units))
! ;    (.unsplice (sh3-common-units))
!   )
! )
!
! ; The actual models
! ; sh2a-nofpu model
! (.splice define-model
!   (name sh2a-nofpu)
!   (comment "sh2a-nofpu reference implementation")
!   (mach sh2a-nofpu)
!   (.unsplice (common-units))
! ;  (unit u-set-sr "Set SR Unit" ()
! ; 0 1 ; issue done
! ; () () () ())
!   (.unsplice (sh2a-nofpu-units))
! )
!
! ; sh2a-fpu model
! (.splice define-model
!   (name sh2a-fpu)
!   (comment "sh2a-fpu reference implementation")
!   (mach sh2a-fpu)
!   (.unsplice (common-units))
!   (.unsplice (common-fp-units))
! ;  (unit u-set-sr "Set SR Unit" ()
! ; 0 1 ; issue done
! ; () () () ())
!   (.unsplice (sh2a-nofpu-units))
!   (.unsplice (sh2a-fpu-units))
! )
!
! ; sh4-nofpu model
! (.splice define-model
!   (name sh4-nofpu)
!   (comment "sh4 nofpu reference implementation")
!   (mach sh4-nofpu)
!   (.unsplice (common-units))
! ;  (.unsplice (sh3-common-units))
!   (.unsplice (sh2a-nofpu-units))
!   (.unsplice (sh4-nofpu-units))
! )
!
! ; sh4 model
! (.splice define-model
!   (name sh4)
!   (comment "sh4 reference implementation")
!   (mach sh4)
!   (.unsplice (common-units))
!   (.unsplice (common-fp-units))
! ;  (.unsplice (sh3-common-units))
!   (.unsplice (sh2a-fpu-units))
!   (.unsplice (sh2a-nofpu-units))
!   (.unsplice (sh4-nofpu-units))
!   (.unsplice (sh4-common-fp-units))
! )
!
! ; sh4a-nofpu model
! (.splice define-model
!   (name sh4a-nofpu)
!   (comment "sh4a no fpu reference implementation")
!   (mach sh4a-nofpu)
!   (.unsplice (common-units))
!   (.unsplice (common-fp-units))
!   (.unsplice (sh2a-nofpu-units))
! ;  (.unsplice (sh3-common-units))
!   (.unsplice (sh4-nofpu-units))
! )
!
! ; sh4a model
! (.splice define-model
!   (name sh4a)
!   (comment "sh4a reference implementation")
!   (mach sh4a)
!   (.unsplice (common-units))
!   (.unsplice (common-fp-units))
!   (.unsplice (sh2a-nofpu-units))
! ;  (.unsplice (sh3-common-units))
!   (.unsplice (sh4-nofpu-units))
!   (.unsplice (sh4-common-fp-units))
! )
!
! ; sh4al model
! (.splice define-model
!   (name sh4al)
!   (comment "sh4al reference implementation")
!   (mach sh4al)
!   (.unsplice (common-units))
!   (.unsplice (common-fp-units))
!   (.unsplice (sh2a-nofpu-units))
! ;  (.unsplice (sh3-common-units))
!   (.unsplice (sh4-nofpu-units))
! )
!
! ; sh5 model
! (.splice define-model
    (name sh5)
!   (comment "sh5 reference implementation")
!   (mach sh5)
!   (.unsplice (common-units))
!   (.unsplice (common-fp-units))
! ;  (.unsplice (sh3-common-units))
!   (.unsplice (sh2a-fpu-units))
!   (.unsplice (sh2a-nofpu-units))
!   (.unsplice (sh4-nofpu-units))
!   (.unsplice (sh4-common-fp-units))
! )
!
! ; sh5-media model
! (.splice define-model
!   (name sh5-media)
!   (comment "sh5 media reference implementation")
    (mach sh5)
! ; ------ some of are not used --- should be separated into
! ; comon_model/compact_model
!   (.unsplice (common-units))
!   (.unsplice (common-fp-units))
! ;  (.unsplice (sh3-common-units))
!   (.unsplice (sh2a-fpu-units))
!   (.unsplice (sh2a-nofpu-units))
!   (.unsplice (sh4-nofpu-units))
!   (.unsplice (sh4-common-fp-units))
! ; --------------------------------------------------------
!   (.unsplice (sh5-media-units))
!   (.unsplice (sh5-media-fp-units))
! )
!
! ; Generate all the remaining models.
! (common-model         sh2)
! (common-model-with-fp sh2e)
! (sh3-model            sh3)
! (sh3e-model           sh3e)
!
! ; Used to generate a timing which is the same for all models
! (define-pmacro (all-models units)
!   ((.splice sh2        (.unsplice units))
!    (.splice sh2e       (.unsplice units))
!    (.splice sh2a-fpu   (.unsplice units))
!    (.splice sh2a-nofpu (.unsplice units))
!    (.splice sh3        (.unsplice units))
!    (.splice sh3e       (.unsplice units))
!    (.splice sh4-nofpu  (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4a-nofpu (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh4al      (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh2e and up.
! (define-pmacro (sh2e-models units)
!   ((.splice sh2e       (.unsplice units))
!    (.splice sh2a-fpu   (.unsplice units))
!    (.splice sh3e       (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh2a and up.
! (define-pmacro (sh2a-nofpu-models units)
!   ((.splice sh2a-fpu   (.unsplice units))
!    (.splice sh2a-nofpu (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4-nofpu  (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh2a and up.
! (define-pmacro (sh2a-fpu-models units)
!   ((.splice sh2a-fpu   (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh3 and up.
! (define-pmacro (sh3-models units)
!   ((.splice sh3        (.unsplice units))
!    (.splice sh3e       (.unsplice units))
!    (.splice sh4-nofpu  (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4a-nofpu (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh4al      (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh3e and up.
! (define-pmacro (sh3e-models units)
!   ((.splice sh3e       (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh4-nofpu and up.
! (define-pmacro (sh4-nofpu-models units)
!   ((.splice sh4-nofpu  (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4a-nofpu (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh4al      (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh4 and up.
! (define-pmacro (sh4-models units)
!   ((.splice sh4   (.unsplice units))
!    (.splice sh4a  (.unsplice units))
!    (.splice sh5   (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh4-nofpu and up.
! (define-pmacro (sh4a-nofpu-models units)
!   ((.splice sh4a-nofpu (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh4al      (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing which is the same for sh5 and up.
! (define-pmacro (sh5-media-models units)
!   ((.splice sh5-media (.unsplice units)))
! )
!
! ; Used to generate timing for SHAD insn
! (define-pmacro (shad-models units)
!   ((.splice sh2a-fpu   (.unsplice units))
!    (.splice sh2a-nofpu (.unsplice units))
!    (.splice sh3        (.unsplice units))
!    (.splice sh3e       (.unsplice units))
!    (.splice sh4-nofpu  (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4a-nofpu (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh4al      (.unsplice units))
!    (.splice sh5        (.unsplice units)))
! )
!
! ; Used to generate a timing for the FSQRT insn
! (define-pmacro (fsqrt-models units)
!   ((.splice sh2a-fpu   (.unsplice units))
!    (.splice sh3e       (.unsplice units))
!    (.splice sh4        (.unsplice units))
!    (.splice sh4a       (.unsplice units))
!    (.splice sh5        (.unsplice units)))
  )
+
 
  ; Hardware elements.
 
  (define-hardware
    (name h-pc)
    (comment "Program counter")
!   (attrs PC PROFILE (ISA compact,media))
    (type pc UDI)
    (get () (raw-reg h-pc))
    (set (newval) (sequence ()
***************
*** 101,107 ****
  (define-hardware
    (name h-gr)
    (comment "General purpose integer registers")
!   (attrs (ISA media,compact))
    (type register DI (64))
    (indices keyword "" (.map -build-greg-name (.iota 64)))
    (get (index)
--- 1058,1064 ----
  (define-hardware
    (name h-gr)
    (comment "General purpose integer registers")
!   (attrs PROFILE (ISA media,compact))
    (type register DI (64))
    (indices keyword "" (.map -build-greg-name (.iota 64)))
    (get (index)
***************
*** 117,123 ****
  (define-hardware
    (name h-grc)
    (comment "General purpose integer registers (SHcompact view)")
!   (attrs VIRTUAL (ISA compact))
    (type register SI (16))
    (indices keyword "" (.map -build-greg-name (.iota 16)))
    (get (index)
--- 1074,1080 ----
  (define-hardware
    (name h-grc)
    (comment "General purpose integer registers (SHcompact view)")
!   (attrs VIRTUAL PROFILE (ISA compact))
    (type register SI (16))
    (indices keyword "" (.map -build-greg-name (.iota 16)))
    (get (index)
***************
*** 140,146 ****
    (raw-reg h-cr index)))
    (set (index newval)
         (if (eq index 0)
!   (set (reg h-sr) newval)
    (set (raw-reg h-cr index) newval)))
  )
 
--- 1097,1103 ----
    (raw-reg h-cr index)))
    (set (index newval)
         (if (eq index 0)
!   (set (raw-reg h-sr) newval)
    (set (raw-reg h-cr index) newval)))
  )
 
***************
*** 163,170 ****
    (comment "Floating point register file bit")
    (attrs (ISA media,compact) VIRTUAL)
    (type register BI)
!   (get () (and (srl (reg h-sr) 14) 1))
!   (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
  )
 
  (define-hardware
--- 1120,1127 ----
    (comment "Floating point register file bit")
    (attrs (ISA media,compact) VIRTUAL)
    (type register BI)
!   (get () (and (srl (reg h-fpscr) 21) 1))
!   (set (newvalue) (set (reg h-fpscr) (or (and (reg h-fpscr) (inv (sll 1 21))) (sll SI newvalue 21))))
  )
 
  (define-hardware
***************
*** 172,179 ****
    (comment "Floating point transfer size bit")
    (attrs (ISA media,compact) VIRTUAL)
    (type register BI)
!   (get () (and (srl (reg h-sr) 13) 1))
!   (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
  )
 
  (define-hardware
--- 1129,1136 ----
    (comment "Floating point transfer size bit")
    (attrs (ISA media,compact) VIRTUAL)
    (type register BI)
!   (get () (and (srl (reg h-fpscr) 20) 1))
!   (set (newvalue) (set (reg h-fpscr) (or (and (reg h-fpscr) (inv (sll 1 20))) (sll SI newvalue 20))))
  )
 
  (define-hardware
***************
*** 181,188 ****
    (comment "Floating point precision bit")
    (attrs (ISA media,compact) VIRTUAL)
    (type register BI)
!   (get () (and (srl (reg h-sr) 12) 1))
!   (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
  )
 
  (define-hardware
--- 1138,1145 ----
    (comment "Floating point precision bit")
    (attrs (ISA media,compact) VIRTUAL)
    (type register BI)
!   (get () (and (srl (reg h-fpscr) 19) 1))
!   (set (newvalue) (set (reg h-fpscr) (or (and (reg h-fpscr) (inv (sll 1 19))) (sll SI newvalue 19))))
  )
 
  (define-hardware
***************
*** 217,223 ****
  (define-hardware
    (name h-fr)
    (comment "Single precision floating point registers")
!   (attrs (ISA media,compact))
    (type register SF (64))
    (indices keyword "" (.map -build-freg-name (.iota 64)))
  )
--- 1174,1180 ----
  (define-hardware
    (name h-fr)
    (comment "Single precision floating point registers")
!   (attrs PROFILE (ISA media,compact))
    (type register SF (64))
    (indices keyword "" (.map -build-freg-name (.iota 64)))
  )
***************
*** 228,236 ****
  (define-hardware
    (name h-fp)
    (comment "Single precision floating point register pairs")
!   (attrs (ISA media,compact))
!   (type register DF (32))
!   (indices keyword "" (.map -build-fpair-name (.iota 32)))
  )
 
  (define-pmacro (-build-fvec-name n) ((.sym fv n) n))
--- 1185,1197 ----
  (define-hardware
    (name h-fp)
    (comment "Single precision floating point register pairs")
!   (attrs VIRTUAL PROFILE (ISA media,compact))
!   (type register SF (64))
!   (indices keyword "" (.map -build-fpair-name
!    (0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
!     32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62)))
!   (get (index) (reg h-fr index))
!   (set (index newval) (set (reg h-fr index) newval))
  )
 
  (define-pmacro (-build-fvec-name n) ((.sym fv n) n))
***************
*** 238,260 ****
  (define-hardware
    (name h-fv)
    (comment "Single precision floating point vectors")
!   (attrs VIRTUAL (ISA media,compact))
!   (type register SF (16))
!   (indices keyword "" (.map -build-fvec-name (.iota 16)))
!   ; Mask with $F to ensure 0 <= index < 15.
!   (get (index) (reg h-fr (mul (and UQI index 15) 4)))
!   (set (index newval) (set (reg h-fr (mul (and UQI index 15) 4)) newval))
  )
 
  (define-hardware
    (name h-fmtx)
    (comment "Single precision floating point matrices")
!   (attrs VIRTUAL (ISA media))
!   (type register SF (4))
!   (indices keyword "" ((mtrx0 0) (mtrx1 1) (mtrx2 2) (mtrx3 3)))
!   ; Mask with $3 to ensure 0 <= index < 4.
!   (get (index) (reg h-fr (mul (and UQI index 3) 16)))
!   (set (index newval) (set (reg h-fr (mul (and UQI index 3) 16)) newval))
  )
 
  (define-pmacro (-build-dreg-name n) ((.sym dr n) n))
--- 1199,1220 ----
  (define-hardware
    (name h-fv)
    (comment "Single precision floating point vectors")
!   (attrs VIRTUAL PROFILE (ISA media,compact))
!   (type register SF (64))
!   (indices keyword "" (.map -build-fvec-name
!    (0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60)))
!   (get (index) (reg h-fr index))
!   (set (index newval) (set (reg h-fr index) newval))
  )
 
  (define-hardware
    (name h-fmtx)
    (comment "Single precision floating point matrices")
!   (attrs VIRTUAL PROFILE (ISA media))
!   (type register SF (64))
!   (indices keyword "" ((mtrx0 0) (mtrx16 16) (mtrx32 32) (mtrx48 48)))
!   (get (index) (reg h-fr index))
!   (set (index newval) (set (reg h-fr index) newval))
  )
 
  (define-pmacro (-build-dreg-name n) ((.sym dr n) n))
***************
*** 262,270 ****
  (define-hardware
    (name h-dr)
    (comment "Double precision floating point registers")
!   (attrs (ISA media,compact) VIRTUAL)
!   (type register DF (32))
!   (indices keyword "" (.map -build-dreg-name (.iota 64)))
    (get (index)
         (subword DF
  (or
--- 1222,1232 ----
  (define-hardware
    (name h-dr)
    (comment "Double precision floating point registers")
!   (attrs VIRTUAL PROFILE (ISA media,compact))
!   (type register DF (64))
!   (indices keyword "" (.map -build-dreg-name
!    (0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
!     32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62)))
    (get (index)
         (subword DF
  (or
***************
*** 279,287 ****
  )
 
  (define-hardware
    (name h-tr)
    (comment "Branch target registers")
!   (attrs (ISA media))
    (type register DI (8))
    (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
  )
--- 1241,1291 ----
  )
 
  (define-hardware
+   (name h-fsd)
+   (comment "Single/Double precision floating point registers")
+   (attrs PROFILE (ISA compact,media) (SH2e-MACH))
+   (type register DF (16))
+   (indices keyword "" (.map -build-freg-name (.iota 16)))
+   (get (index)
+        (if DF prbit (reg h-drc index) (fext DF (reg h-fr index))))
+   (set (index newval)
+        (if prbit
+   (set (reg h-drc index) newval)
+   (set (reg h-frc index) (ftrunc SF newval))))
+ )
+
+ (define-pmacro (even x) (eq (and x 1) 0))
+ (define-pmacro (odd x)  (eq (and x 1) 1))
+ (define-pmacro (extd x) (odd x))
+
+ (define-hardware
+   (name h-fmov)
+   (comment "floating point registers for fmov")
+   (attrs PROFILE (ISA compact,media) (SH2e-MACH))
+   (type register DF (16))
+   (indices keyword "" (.map -build-freg-name (.iota 16)))
+   (get (index)
+        (if DF (not szbit)
+   ; single precision operation
+   (fext DF (reg h-frc index))
+   ; double or extended operation
+   (if DF (extd index)
+       (reg h-xd (and index (inv 1)))
+       (reg h-dr index))))
+   (set (index newval)
+        (if (not szbit)
+   ; single precision operation
+   (set (reg h-frc index) (ftrunc SF newval))
+   ; double or extended operation
+   (if (extd index)
+       (set (reg h-xd (and index (inv 1))) newval)
+       (set (reg h-dr index) newval))))
+ )
+
+ (define-hardware
    (name h-tr)
    (comment "Branch target registers")
!   (attrs (ISA media) PROFILE)
    (type register DI (8))
    (indices keyword "" ((tr0 0) (tr1 1) (tr2 2) (tr3 3) (tr4 4) (tr5 5) (tr6 6) (tr7 7)))
  )
Index: cgen/cpu/sh64-compact.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/sh64-compact.cpu,v
retrieving revision 1.4
diff -c -p -r1.4 sh64-compact.cpu
*** cgen/cpu/sh64-compact.cpu 21 May 2003 14:10:46 -0000 1.4
--- cgen/cpu/sh64-compact.cpu 22 Aug 2006 17:22:28 -0000
***************
*** 1,17 ****
  ; SuperH SHcompact instruction set description.  -*- Scheme -*-
! ; Copyright (C) 2000 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
  ; dshcf -- define-normal-sh-compact-field
 
! (define-pmacro (dshcf xname xcomment ignored xstart xlength)
!   (dnf xname xcomment ((ISA compact)) xstart xlength))
 
  ; dshcop -- define-normal-sh-compact-operand
 
! (define-pmacro (dshcop xname xcomment ignored xhardware xfield)
!   (dnop xname xcomment ((ISA compact)) xhardware xfield))
 
 
  ; SHcompact-specific attributes.
--- 1,17 ----
  ; SuperH SHcompact instruction set description.  -*- Scheme -*-
! ; Copyright (C) 2000, 2006 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
  ; dshcf -- define-normal-sh-compact-field
 
! (define-pmacro (dshcf xname xcomment xattrs xstart xlength)
!   (dnf xname xcomment (.splice (ISA compact) (.unsplice xattrs)) xstart xlength))
 
  ; dshcop -- define-normal-sh-compact-operand
 
! (define-pmacro (dshcop xname xcomment xattrs xhardware xfield)
!   (dnop xname xcomment (.splice (ISA compact) (.unsplice xattrs)) xhardware xfield))
 
 
  ; SHcompact-specific attributes.
***************
*** 30,35 ****
--- 30,63 ----
    (comment "floating point instruction")
  )
 
+ (define-attr
+   (for insn)
+   (type boolean)
+   (name 32-BIT-INSN)
+   (comment "32 bit insn")
+ )
+
+ ; Attributes to describe categories of insns
+ (define-attr
+   (for insn)
+   (type enum)
+   (name SH4-GROUP)
+   (comment "sh4 insn groups")
+   ; The order of declaration is significant. Table lookup is
+   ; performed using these as indices.
+   (values NONE MT EX BR LS FE CO MAX)
+ )
+
+ (define-attr
+   (for insn)
+   (type enum)
+   (name SH4A-GROUP)
+   (comment "sh4a insn groups")
+   ; The order of declaration is significant. Table lookup is
+   ; performed using these as indices.
+   (values NONE MT EX BR LS FE CO MAX)
+ )
+
  (define-keyword
    (name frc-names)
    (attrs (ISA compact))
***************
*** 63,69 ****
  (define-hardware
    (name h-frc)
    (comment "Single precision floating point registers")
!   (attrs VIRTUAL (ISA compact))
    (indices extern-keyword frc-names)
    (type register SF (16))
    (get (index) (reg h-fr (add (front) index)))
--- 91,97 ----
  (define-hardware
    (name h-frc)
    (comment "Single precision floating point registers")
!   (attrs VIRTUAL PROFILE (ISA compact))
    (indices extern-keyword frc-names)
    (type register SF (16))
    (get (index) (reg h-fr (add (front) index)))
***************
*** 73,79 ****
  (define-hardware
    (name h-drc)
    (comment "Double precision floating point registers")
!   (attrs VIRTUAL (ISA compact))
    (indices extern-keyword drc-names)
    (type register DF (8))
    (get (index) (reg h-dr (add (front) index)))
--- 101,107 ----
  (define-hardware
    (name h-drc)
    (comment "Double precision floating point registers")
!   (attrs VIRTUAL PROFILE (ISA compact))
    (indices extern-keyword drc-names)
    (type register DF (8))
    (get (index) (reg h-dr (add (front) index)))
***************
*** 110,127 ****
    (set (index newval) (set (reg h-fr (add (front) index)) newval))
  )
 
! (define-hardware
!   (name h-fpccr)
!   (comment "SHcompact floating point status/control register")
!   (attrs VIRTUAL (ISA compact))
!   (type register SI)
!   (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21)))
!   (set (newvalue) (sequence ()
!    (set (reg h-fpscr) newvalue)
!    (set prbit (and (srl newvalue 19) 1))
!    (set szbit (and (srl newvalue 20) 1))
!    (set frbit (and (srl newvalue 21) 1))))
! )
 
  (define-hardware
    (name h-gbr)
--- 138,156 ----
    (set (index newval) (set (reg h-fr (add (front) index)) newval))
  )
 
! ; not needed? Using h-fpscr directly
! ;(define-hardware
! ;  (name h-fpccr)
! ;  (comment "SHcompact floating point status/control register")
! ;  (attrs VIRTUAL (ISA compact))
! ;  (type register SI)
! ;  (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21)))
! ;  (set (newvalue) (sequence ()
! ;    (set (reg h-fpscr) newvalue)
! ;    (set prbit (and (srl newvalue 19) 1))
! ;    (set szbit (and (srl newvalue 20) 1))
! ;    (set frbit (and (srl newvalue 21) 1))))
! ;)
 
  (define-hardware
    (name h-gbr)
***************
*** 133,138 ****
--- 162,176 ----
  )
 
  (define-hardware
+   (name h-vbr)
+   (comment "Vector base register")
+   (attrs VIRTUAL (ISA compact))
+   (type register SI)
+   (get () (subword SI (raw-reg h-gr 20) 1))
+   (set (newval) (set (raw-reg h-gr 20) (ext DI newval)))
+ )
+
+ (define-hardware
    (name h-pr)
    (comment "Procedure link register")
    (attrs VIRTUAL (ISA compact))
***************
*** 169,238 ****
  )
 
 
! (dshcf f-op4     "Opcode (4 bits)"         ()  15   4)
! (dshcf f-op8     "Opcode (8 bits)"         ()  15   8)
! (dshcf f-op16    "Opcode (16 bits)"        ()  15  16)
!
! (dshcf f-sub4    "Sub opcode (4 bits)"     ()   3   4)
! (dshcf f-sub8    "Sub opcode (8 bits)"     ()   7   8)
! (dshcf f-sub10   "Sub opcode (10 bits)"    ()   9  10)
!
! (dshcf f-rn      "Register selector n"     ()  11   4)
! (dshcf f-rm      "Register selector m"     ()   7   4)
!
! (dshcf f-8-1     "One bit at bit 8"        ()   8   1)
 
! (df  f-disp8  "Displacement (8 bits)"  ((ISA compact) PCREL-ADDR) 7 8 INT
       ((value pc) (sra SI value 1))
       ((value pc) (add SI (sll SI value 1) (add pc 4))))
 
! (df  f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 11 12 INT
       ((value pc) (sra SI value 1))
       ((value pc) (add SI (sll SI value 1) (add pc 4))))
 
! (dshcf f-imm8    "Immediate (8 bits)"      ()   7   8)
! (dshcf f-imm4    "Immediate (4 bits)"      ()   3   4)
 
! (df f-imm4x2     "Immediate (4 bits)"      ((ISA compact)) 3 4 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-imm4x4     "Immediate (4 bits)"      ((ISA compact)) 3 4 UINT
      ((value pc) (srl SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df f-imm8x2     "Immediate (8 bits)"      ((ISA compact)) 7 8 UINT
      ((value pc) (sra SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-imm8x4     "Immediate (8 bits)"      ((ISA compact)) 7 8 UINT
      ((value pc) (sra SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df f-dn "Double selector n" ((ISA compact)) 11 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-dm         "Double selector m"       ((ISA compact)) 7 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-vn         "Vector selector n"       ((ISA compact)) 11 2 UINT
      ((value pc) (srl SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df f-vm         "Vector selector m"       ((ISA compact)) 9 2 UINT
      ((value pc) (srl SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df f-xn         "Extended selector n"     ((ISA compact)) 11 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (add SI (sll SI value 1) 1)))
 
! (df f-xm         "Extended selector m"     ((ISA compact)) 7 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (add SI (sll SI value 1) 1)))
 
 
  ; Operands.
 
--- 207,301 ----
  )
 
 
! (dshcf f-op4     "Opcode (4 bits)"         ()   0   4)
! (dshcf f-op8     "Opcode (8 bits)"         ()   0   8)
! (dshcf f-op16    "Opcode (16 bits)"        ()   0  16)
!
! (dshcf f-sub4    "Sub opcode (4 bits)"     ()  12   4)
! (dshcf f-sub8    "Sub opcode (8 bits)"     ()   8   8)
! (dshcf f-sub10   "Sub opcode (10 bits)"    ()   6  10)
!
! (dshcf f-rn      "Register selector n"     ()   4   4)
! (dshcf f-rm      "Register selector m"     ()   8   4)
!
! (dshcf f-7-1     "One bit at bit 8"        ()   7   1)
! (dshcf f-11-1    "One bit at bit 11"       ()  11   1)
! (dshcf f-16-4    "4 bits at bit 16"        ()  16   4)
 
! (df  f-disp8  "Displacement (8 bits)"  ((ISA compact) PCREL-ADDR) 8 8 INT
       ((value pc) (sra SI value 1))
       ((value pc) (add SI (sll SI value 1) (add pc 4))))
 
! (df  f-disp12 "Displacement (12 bits)" ((ISA compact) PCREL-ADDR) 4 12 INT
       ((value pc) (sra SI value 1))
       ((value pc) (add SI (sll SI value 1) (add pc 4))))
 
! (dshcf f-imm8    "Immediate (8 bits)"      ()   8   8)
! (dshcf f-imm4    "Immediate (4 bits)"      ()  12   4)
 
! (df f-imm4x2     "Immediate (4 bits)"      ((ISA compact)) 12 4 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-imm4x4     "Immediate (4 bits)"      ((ISA compact)) 12 4 UINT
      ((value pc) (srl SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df f-imm8x2     "Immediate (8 bits)"      ((ISA compact)) 8 8 UINT
      ((value pc) (sra SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-imm8x4     "Immediate (8 bits)"      ((ISA compact)) 8 8 UINT
      ((value pc) (sra SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df  f-imm12x4 "Displacement (12 bits)" ((ISA compact)) 20 12 INT
!      ((value pc) (sra SI value 2))
!      ((value pc) (sll SI value 2)))
!
! (df  f-imm12x8 "Displacement (12 bits)" ((ISA compact)) 20 12 INT
!      ((value pc) (sra SI value 3))
!      ((value pc) (sll SI value 3)))
!
! (df f-dn "Double selector n" ((ISA compact))  4 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-dm         "Double selector m"       ((ISA compact)) 8 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (sll SI value 1)))
 
! (df f-vn         "Vector selector n"       ((ISA compact)) 4 2 UINT
      ((value pc) (srl SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df f-vm         "Vector selector m"       ((ISA compact)) 6 2 UINT
      ((value pc) (srl SI value 2))
      ((value pc) (sll SI value 2)))
 
! (df f-xn         "Extended selector n"     ((ISA compact)) 4 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (add SI (sll SI value 1) 1)))
 
! (df f-xm         "Extended selector m"     ((ISA compact)) 8 3 UINT
      ((value pc) (srl SI value 1))
      ((value pc) (add SI (sll SI value 1) 1)))
 
+ (df f-imm20-hi "imm20 hi" ((ISA compact))  8  4  INT #f #f)
+ (df f-imm20-lo "imm20 lo" ((ISA compact)) 16 16 UINT #f #f)
+ (define-multi-ifield
+   (name f-imm20)
+   (comment "20 bit immediate")
+   (attrs (ISA compact))
+   (mode INT)
+   (subfields f-imm20-hi f-imm20-lo)
+   (insert (sequence ()
+    (set (ifield f-imm20-lo) (and (ifield f-imm20) #xffff))
+    (set (ifield f-imm20-hi) (sra (ifield f-imm20) 16))))
+   (extract (set (ifield f-imm20)
+ (or (sll (ifield f-imm20-hi) 16) (ifield f-imm20-lo))))
+   )
+
 
  ; Operands.
 
***************
*** 242,247 ****
--- 305,314 ----
 
  (dshcop frn    "Single precision register"              ()   h-frc   f-rn)
  (dshcop frm    "Single precision register"              ()   h-frc   f-rm)
+ (dshcop fr0    "Single precision register 0"            ()   h-frc   0)
+
+ (dshcop fmovn  "Register for fmov"                      ((SH2e-MACH)) h-fmov f-rn)
+ (dshcop fmovm  "Register for fmov"                      ((SH2e-MACH)) h-fmov f-rm)
 
  (dshcop fvn    "Left floating point vector"             ()   h-fvc   f-vn)
  (dshcop fvm    "Right floating point vector"            ()   h-fvc   f-vm)
***************
*** 252,257 ****
--- 319,325 ----
  (dshcop imm4   "Immediate value (4 bits)" ()   h-sint  f-imm4)
  (dshcop imm8   "Immediate value (8 bits)"               ()   h-sint  f-imm8)
  (dshcop uimm8  "Immediate value (8 bits unsigned)"      ()   h-uint  f-imm8)
+ (dshcop imm20  "Immediate value (20 bits)"              ()   h-sint  f-imm20)
 
  (dshcop imm4x2 "Immediate value (4 bits, 2x scale)"     ()   h-uint  f-imm4x2)
  (dshcop imm4x4 "Immediate value (4 bits, 4x scale)"     ()   h-uint  f-imm4x4)
***************
*** 260,273 ****
 
  (dshcop disp8  "Displacement (8 bits)"                  ()   h-iaddr f-disp8)
  (dshcop disp12 "Displacement (12 bits)"                 ()   h-iaddr f-disp12)
 
  (dshcop rm64   "Register m (64 bits)"                   ()   h-gr    f-rm)
  (dshcop rn64   "Register n (64 bits)"                   ()   h-gr    f-rn)
 
  (dshcop gbr    "Global base register"                   ()   h-gbr   f-nil)
  (dshcop pr     "Procedure link register"                ()   h-pr    f-nil)
 
! (dshcop fpscr  "Floating point status/control register" ()   h-fpccr f-nil)
 
  (dshcop tbit   "Condition code flag"                    ()   h-tbit  f-nil)
  (dshcop sbit   "Multiply-accumulate saturation flag"    ()   h-sbit  f-nil)
--- 328,344 ----
 
  (dshcop disp8  "Displacement (8 bits)"                  ()   h-iaddr f-disp8)
  (dshcop disp12 "Displacement (12 bits)"                 ()   h-iaddr f-disp12)
+ (dshcop imm12x4 "Displacement (12 bits)"                ()   h-sint  f-imm12x4)
+ (dshcop imm12x8 "Displacement (12 bits)"                ()   h-sint  f-imm12x8)
 
  (dshcop rm64   "Register m (64 bits)"                   ()   h-gr    f-rm)
  (dshcop rn64   "Register n (64 bits)"                   ()   h-gr    f-rn)
 
  (dshcop gbr    "Global base register"                   ()   h-gbr   f-nil)
+ (dshcop vbr    "Vector base register"                   ()   h-vbr   f-nil)
  (dshcop pr     "Procedure link register"                ()   h-pr    f-nil)
 
! (dshcop fpscr  "Floating point status/control register" ()   h-fpscr f-nil)
 
  (dshcop tbit   "Condition code flag"                    ()   h-tbit  f-nil)
  (dshcop sbit   "Multiply-accumulate saturation flag"    ()   h-sbit  f-nil)
***************
*** 282,493 ****
  (dshcop macl   "Multiply-accumulate low register"       ()   h-macl  f-nil)
  (dshcop mach   "Multiply-accumulate high register"      ()   h-mach  f-nil)
 
-
  (define-operand (name fsdm) (comment "bar")
!   (attrs (ISA compact)) (type h-frc) (index f-rm) (handlers (parse "fsd")))
 
  (define-operand (name fsdn) (comment "bar")
!   (attrs (ISA compact)) (type h-frc) (index f-rn))
 
 
  ; Cover macro to dni to indicate these are all SHcompact instructions.
  ; dshmi: define-normal-sh-compact-insn
 
! (define-pmacro (dshci xname xcomment xattrs xsyntax xformat xsemantics)
    (define-insn
      (name (.sym xname -compact))
      (comment xcomment)
      (.splice attrs (.unsplice xattrs) (ISA compact))
      (syntax xsyntax)
      (format xformat)
!     (semantics xsemantics)))
!
! (define-pmacro (dr operand) (reg h-dr (index-of operand)))
! (define-pmacro (xd x) (reg h-xd (and (index-of x) (inv QI 1))))
 
  (dshci add "Add"
!        ()
         "add $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 12))
!        (set rn (add rn rm)))
 
  (dshci addi "Add immediate"
!        ()
         "add #$imm8, $rn"
         (+ (f-op4 7) rn imm8)
!        (set rn (add rn (ext SI (and QI imm8 255)))))
 
  (dshci addc "Add with carry"
!        ()
         "addc $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 14))
         (sequence ((BI flag))
  (set flag (add-cflag rn rm tbit))
  (set rn (addc rn rm tbit))
! (set tbit flag)))
 
  (dshci addv "Add with overflow"
!        ()
         "addv $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 15))
         (sequence ((BI t))
  (set t (add-oflag rn rm 0))
  (set rn (add rn rm))
! (set tbit t)))
 
  (dshci and "Bitwise AND"
!        ()
         "and $rm64, $rn64"
         (+ (f-op4 2) rn64 rm64 (f-sub4 9))
!        (set rn64 (and rm64 rn64)))
 
  (dshci andi "Bitwise AND immediate"
!        ()
         "and #$uimm8, r0"
         (+ (f-op8 #xc9) uimm8)
!        (set r0 (and r0 (zext DI uimm8))))
 
  (dshci andb "Bitwise AND memory byte"
!        ()
         "and.b #$imm8, @(r0, gbr)"
         (+ (f-op8 #xcd) imm8)
         (sequence ((DI addr) (UQI data))
  (set addr (add r0 gbr))
  (set data (and (mem UQI addr) imm8))
! (set (mem UQI addr) data)))
 
  (dshci bf "Conditional branch"
!        ()
         "bf $disp8"
         (+ (f-op8 #x8b) disp8)
         (if (not tbit)
!   (set pc disp8)))
 
  (dshci bfs "Conditional branch with delay slot"
!        ()
         "bf/s $disp8"
         (+ (f-op8 #x8f) disp8)
         (if (not tbit)
!   (delay 1 (set pc disp8))))
 
  (dshci bra "Branch"
!        ()
         "bra $disp12"
         (+ (f-op4 10) disp12)
!        (delay 1 (set pc disp12)))
 
  (dshci braf "Branch far"
!        ()
         "braf $rn"
         (+ (f-op4 0) rn (f-sub8 35))
!        (delay 1 (set pc (add (ext DI rn) (add pc 4)))))
 
  (dshci brk "Breakpoint"
!        ()
         "brk"
         (+ (f-op16 59))
!        (c-call "sh64_break" pc))
 
  (dshci bsr "Branch to subroutine"
!        ()
         "bsr $disp12"
         (+ (f-op4 11) disp12)
!        (delay 1 (sequence ()
!  (set pr (add pc 4))
!  (set pc disp12))))
 
  (dshci bsrf "Branch to far subroutine"
!        ()
         "bsrf $rn"
         (+ (f-op4 0) rn (f-sub8 3))
!        (delay 1 (sequence ()
!  (set pr (add pc 4))
!  (set pc (add (ext DI rn) (add pc 4))))))
         
  (dshci bt "Conditional branch"
!        ()
         "bt $disp8"
         (+ (f-op8 #x89) disp8)
         (if tbit
!   (set pc disp8)))
 
  (dshci bts "Conditional branch with delay slot"
!        ()
         "bt/s $disp8"
         (+ (f-op8 #x8d) disp8)
         (if tbit
!   (delay 1 (set pc disp8))))
 
  (dshci clrmac "Clear MACL and MACH"
!        ()
         "clrmac"
         (+ (f-op16 40))
         (sequence ()
  (set macl 0)
! (set mach 0)))
 
  (dshci clrs "Clear S-bit"
!        ()
         "clrs"
         (+ (f-op16 72))
!        (set sbit 0))
 
  (dshci clrt "Clear T-bit"
!        ()
         "clrt"
         (+ (f-op16 8))
!        (set tbit 0))
 
  (dshci cmpeq "Compare if equal"
!        ()
         "cmp/eq $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 0))
!        (set tbit (eq rm rn)))
 
  (dshci cmpeqi "Compare if equal (immediate)"
!        ()
         "cmp/eq #$imm8, r0"
         (+ (f-op8 #x88) imm8)
!        (set tbit (eq r0 (ext SI (and QI imm8 255)))))
 
  (dshci cmpge "Compare if greater than or equal"
!        ()
         "cmp/ge $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 3))
!        (set tbit (ge rn rm)))
 
  (dshci cmpgt "Compare if greater than"
!        ()
         "cmp/gt $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 7))
!        (set tbit (gt rn rm)))
 
  (dshci cmphi "Compare if greater than (unsigned)"
!        ()
         "cmp/hi $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 6))
!        (set tbit (gtu rn rm)))
 
  (dshci cmphs "Compare if greater than or equal (unsigned)"
!        ()
         "cmp/hs $rm, $rn"
         (+ (f-op4 3) rn rm (f-sub4 2))
!        (set tbit (geu rn rm)))
 
  (dshci cmppl "Compare if greater than zero"
!    
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Re: [patch][rfc] sh64: Add Pipeline Modelling and SID Support

Michael Snyder-4
On Tue, 2006-08-22 at 14:18 -0400, Dave Brolley wrote:

> I would like to commit this patch which does the following for the sh64
> target:
>
> 1) Add support for generating a SID simulator.
> 2) Add pipeline modelling for all sh machines (currently used only by SID).
> 3) Adds support for some previously unsupported insns (both SID and
> sim/sh64).
>
> I will submit the changes needed for sim/sh64 and sid separately. The
> sim/sh simulator is currently not generated by CGEN.
>
> NOTES:
> o This is a patch against the existing sh.cpu, sh64-compact.cpu and
> sh64-media.cpu in the cgen/cpu directory and which are currently used to
> generate the sh64 simulator in sim/sh64. .cpu files also exist in the  
> cpu directory, but they appear to be out of date compared to the ones in
> cgen/cpu. Any clarification regarding which files are being actively
> maintained would be much appreciated!
>
> o The new files sh-sid.cpu and sh-sim.cpu provide pmacros for handling
> the differences between generating sid and sim.
>
> Comments, concerns and, ultimately, approval to commit please!

Hmmm, sh sim doesn't currently seem to have a maintainer.

Would you like the job?   ;-)


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Re: [patch][rfc] sh64: Add Pipeline Modelling and SID Support

Dave Brolley-2
In reply to this post by Dave Brolley-2
Having been accepted as the maintainer of the sh64 simulator, I have now
committed this patch.

Dave Brolley wrote:
> I would like to commit this patch which does the following for the
> sh64 target:
>
> 1) Add support for generating a SID simulator.
> 2) Add pipeline modelling for all sh machines (currently used only by
> SID).
> 3) Adds support for some previously unsupported insns (both SID and
> sim/sh64).
>