[patch][rfa] Representation of ISA Attribute in CGEN

classic Classic list List threaded Threaded
2 messages Options
Reply | Threaded
Open this post in threaded view
|

[patch][rfa] Representation of ISA Attribute in CGEN

Dave Brolley-2
Hi,

These changes have been in our local tree for a few years now and were
developed for an internal port which requires *much* more than 32 ISAs
or even 64 ISAs. These changes could be of benifit to others, so I would
like to submit them for approval.

Currently, ISA is represented as an integer, like all the other
non-boolean attributes. It is a bit mask with each bit representing
whether a particular ISA is supported. Our port requires that there be
no fixed limit on the number of ISAs, and so, we developed an open-ended
representation for a bitset using a bitstring and a length. It is called
CGEN_BITSET and is declared in include/opcode/cgen-bitset.h and
supported by several new functions in opcodes/cgen-opc.c. All
manipulation of these bitsets is done using these functions which hide
the internal representation. See cgen-bitset.h (attached) for a
description of the implementation

The patch has 3 parts:
1) Extension of CGEN_ATTR_VALUE_TYPE to be a union allowing the use of
CGEN_BITSET as well as its supporting macros.

2) Changes to CGEN so that it generates code to correctly access and
initialize the new definition of CGEN_ATTR_VALUE_TYPE and to use the
proper cover functions when manipulating ISAs.

3) Changes to hand written portions of existing opcodes, sim and sid
ports as in 2). Fortunately, the use of existing CGEN macros made these
changes minimal.

I have also included in the patch the regenerated source for the frv
port so that you can see the effect on the generated code. None of the
generated code for existing sid ports is affected.

One natural extension of this work would be use the same representation
for all bitset attributes in CGEN. I believe that MACH is the only other
one at this time.

Seeking comments and approval to commit.

Thanks,
Dave

cgen/ChangeLog:
2005-09-19  Dave Brolley  <[hidden email]>

        * attr.scm (gen-value-for-defn-raw): New methods.
        (gen-value-for-defn): Don't test for 'SID-SIMULATOR. Call
        gen-value-for-defn-raw.
        * sid.scm (gen-obj-attr-sid-defn): Call gen-value-for-defn-raw.

2002-12-13  Dave Brolley  <[hidden email]>

        * utils-cgen.scm (gen-attr-type): Moved from sid.scm.
        (-gen-attr-accessors): New function.
        (gen-obj-attr-defn): Update terminating initializer.
        (gen-obj-attr-end-defn): New function.
        * sid.scm (gen-attr-type): Moved to utils-cgen.scm.
        * sid-cpu.scm (cgen-desc.h): Generate code to include
        "opcode/cgen-bitset.h"
        * intrinsics.scm (kept-insn-isas): Correct the extraction of the isa
        name.
        * desc.scm ('gen-defn): Update terminating initializer.
        * desc-cpu.scm (gen-ifld-decls): Call -gen-attr-accessors. Update
        terminatinig initializer.
        (gen-hw-decls): Ditto.
        (gen-operand-decls): Ditto.
        (gen-insn-decls): Ditto.
        (-gen-hash-defines): Generate code to include "opcde/cgen-bitset.h"
        (gen-insn-table): Update terminating initializer.
        (-gen-cpu-open): Update generation of @arch@_cgen_rebuild_tables,
        @arch@_cgen_cpu_open, @arch@_cgen_cpu_close.
        * attr.scm (charmask-bytes): New function.
        (bitset-attr->charmask): New function.
        (<bitset-attribute>): Handle isa-attributes specially. Also handle
        differences for SID-SIMULATOR.
        (<integer-attribute>): Handle differences for SID-SIMULATOR.
        (<enum-attribute>): Ditto.

include/ChangeLog:
2003-09-29  Dave Brolley  <[hidden email]>

        * dis-asm.h (disassemble_info): insn_sets now (void *) to allow for
        more exotic underlying types to be used.

include/opcode/ChangeLog:
2005-02-16  Dave Brolley  <[hidden email]>

        * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
        cgen_isa_mask_* to cgen_bitset_*.
        * cgen.h: Likewise.

2003-10-21  Richard Sandiford  <[hidden email]>

        * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
        (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
        (CGEN_CPU_TABLE): Make isas a ponter.

2003-09-29  Dave Brolley  <[hidden email]>

        * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
        (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
        (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.

2002-12-13  Dave Brolley  <[hidden email]>

        * cgen.h (symcat.h): #include it.
        (cgen-bitset.h): #include it.
        (CGEN_ATTR_VALUE_TYPE): Now a union.
        (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
        (CGEN_ATTR_ENTRY): 'value' now unsigned.
        (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
        * cgen-bitset.h: New file.

opcodes/ChangeLog:
2005-09-19  Dave Brolley  <[hidden email]>

        * disassemble.c (disassemble_init_for_target): Add 'break' to case for
        bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for
        bfd_arch_m32c case.

2005-02-16  Dave Brolley  <[hidden email]>

        * cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
        cgen_isa_mask_* to cgen_bitset_*.
        * cgen-opc.c: Likewise.

2003-11-28  Richard Sandiford  <[hidden email]>

        * cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas.
        * *-dis.c: Regenerate.

2003-06-05  DJ Delorie <[hidden email]>

        * cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign
        it, as it may point to a reused buffer. Set prev_isas when we
        change cpus.

2002-12-13  Dave Brolley  <[hidden email]>

        * cgen-opc.c (cgen_isa_mask_create): New support function for
        CGEN_ISA_MASK.
        (cgen_isa_mask_init): Ditto.
        (cgen_isa_mask_clear): Ditto.
        (cgen_isa_mask_add): Ditto.
        (cgen_isa_mask_set): Ditto.
        (cgen_isa_supported): Ditto.
        (cgen_isa_mask_compare): Ditto.
        (cgen_isa_mask_intersection): Ditto.
        (cgen_isa_mask_copy): Ditto.
        (cgen_isa_mask_combine): Ditto.
        * cgen-dis.in (libiberty.h): #include it.
        (isas): Renamed from 'isa' and now (CGEN_ISA_MASK *).
        (print_insn_@arch@): Use CGEN_ISA_MASK and support functions.
        * Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm.
        * Makefile.in: Regenerated.

sid/component/cgen-cpu/ChangeLog:
2003-10-07  Dave Brolley  <[hidden email]>

        * tracedis.cxx (cgen_disassemble): Rename isa_mask to isas. Now
        (CGEN_ISA_MASK*).
        * tracedis.h (opcode/cgen-bitset.h): #include it.
        (cgen_disassemble): Rename isa_mask to isas. Now
        (CGEN_ISA_MASK*).
        (cgen_bi_endian_cpu::disassemble): 'isas' now (CGEN_ISA_MASK *).
        * cgen-cpu.h (opcode/cgen-bitset.h): #include it.
        (cgen_bi_endian_cpu::disassemble): 'isas' now (CGEN_ISA_MASK *).
        * compCGEN.cxx (cgen_disassemble): Rename isa_mask to isas. Now
        (CGEN_ISA_MASK*).

cpu/ChangeLog:
2003-09-24  Dave Brolley  <[hidden email]>

        * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
        CGEN_ATTR_VALUE_TYPE.
        * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE.
        Use cgen_bitset_intersect_p.

gas/ChangeLog:
2005-09-19  Dave Brolley  <[hidden email]>

        * config/tc-m32c.c (default_isa): New static variable.
        (m32c_isa): Now of type CGEN_BITSET.
        (md_begin): Pass &m32c_isa to m32c_cgen_cpu_open.

sim/frv/ChangeLog:
2003-09-29  Dave Brolley  <[hidden email]>

        * frv-sim.h: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
        CGEN_ATTR_VALUE_TYPE.
        * mloop.in: Ditto.
        * pipeline.c: Ditto.
        * traps.c: Ditto.


/* Header file the type CGEN_BITSET.

Copyright 2002, 2005 Free Software Foundation, Inc.

This file is part of GDB, the GNU debugger, and the GNU Binutils.

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
#ifndef CGEN_BITSET_H
#define CGEN_BITSET_H

#ifdef __cplusplus
extern "C" {
#endif

/* A bitmask represented as a string.
   Each member of the set is represented as a bit
   in the string. Bytes are indexed from left to right in the string and
   bits from most significant to least within each byte.

   For example, the bit representing member number 6 is (set->bits[0] & 0x02).
*/
typedef struct cgen_bitset
{
  unsigned length;
  char *bits;
} CGEN_BITSET;

extern CGEN_BITSET *cgen_bitset_create PARAMS ((unsigned));
extern void cgen_bitset_init PARAMS ((CGEN_BITSET *, unsigned));
extern void cgen_bitset_clear PARAMS ((CGEN_BITSET *));
extern void cgen_bitset_add PARAMS ((CGEN_BITSET *, unsigned));
extern void cgen_bitset_set PARAMS ((CGEN_BITSET *, unsigned));
extern int cgen_bitset_compare PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
extern void cgen_bitset_union PARAMS ((CGEN_BITSET *, CGEN_BITSET *, CGEN_BITSET *));
extern int cgen_bitset_intersect_p PARAMS ((CGEN_BITSET *, CGEN_BITSET *));
extern int cgen_bitset_contains PARAMS ((CGEN_BITSET *, unsigned));
extern CGEN_BITSET *cgen_bitset_copy PARAMS ((CGEN_BITSET *));

#ifdef __cplusplus
} // extern "C"
#endif

#endif

? include/opcode/cgen-bitset.h
Index: cgen/attr.scm
===================================================================
RCS file: /cvs/src/src/cgen/attr.scm,v
retrieving revision 1.3
diff -c -p -r1.3 attr.scm
*** cgen/attr.scm 16 Jul 2003 05:35:47 -0000 1.3
--- cgen/attr.scm 19 Sep 2005 19:48:42 -0000
***************
*** 1,5 ****
  ; Attributes.
! ; Copyright (C) 2000 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
--- 1,5 ----
  ; Attributes.
! ; Copyright (C) 2000, 2003 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
***************
*** 613,618 ****
--- 613,654 ----
    (map string->symbol (string-cut (->string x) #\,))
  )
 
+ ; Generate a list representing a bit mask of the indices of 'values'
+ ; within 'all-values'. Each element in the resulting list represents a byte.
+ ; Both bits and bytes are indexed from left to right starting at 0
+ ; with 8 bits in a byte.
+ (define (charmask-bytes values all-values vec-length)
+   (logit 3 "charmask-bytes for " values " " all-values "\n")
+   (let ((result (make-vector vec-length 0))
+ (indices (map (lambda (name)
+ (list-ref (map cadr all-values)
+  (element-lookup-index name (map car all-values) 0)))
+      values)))
+     (logit 3 "indices: " indices "\n")
+     (for-each (lambda (x)
+ (let* ((byteno (quotient x 8))
+       (bitno (- 7 (remainder x 8)))
+       (byteval (logior (vector-ref result byteno)
+ (ash 1 bitno))))
+  (vector-set! result byteno byteval)))
+      indices)
+     (logit 3 "result: " (vector->list result) "\n")
+     (vector->list result))
+ )
+
+ ; Convert a bitset value into a bit string based on the
+ ; index of each member in values
+ (define (bitset-attr->charmask value values)
+   (let* ((values-names (map car values))
+ (values-values (map cadr values))
+ (vec-length (+ 1 (quotient (apply max values-values) 8))))
+     (string-append "{ " (number->string vec-length) ", \""
+   (string-map (lambda (x)
+ (string-append "\\x" (number->hex x)))
+       (charmask-bytes (bitset-attr->list value)
+       values vec-length))
+   "\" }"))
+ )
  ; Return the enum of ATTR-NAME for type TYPE.
  ; TYPE is one of 'ifld, 'hw, 'operand, 'insn.
 
***************
*** 916,922 ****
  ; (maybe utils-cgen.scm?) and there's only a few of them.
 
  (method-make!
!  <boolean-attribute> 'gen-value-for-defn
   (lambda (self value)
     (if (not value)
         "0"
--- 952,958 ----
  ; (maybe utils-cgen.scm?) and there's only a few of them.
 
  (method-make!
!  <boolean-attribute> 'gen-value-for-defn-raw
   (lambda (self value)
     (if (not value)
         "0"
***************
*** 925,954 ****
  )
 
  (method-make!
   <bitset-attribute> 'gen-value-for-defn
   (lambda (self value)
!    (string-drop1
!     (string-upcase
!      (string-map (lambda (x)
!   (string-append "|(1<<"
!  (gen-sym self)
!  "_" (gen-c-symbol x) ")"))
! (bitset-attr->list value)))))
  )
 
  (method-make!
   <integer-attribute> 'gen-value-for-defn
   (lambda (self value)
!    (number->string value))
  )
 
  (method-make!
!  <enum-attribute> 'gen-value-for-defn
   (lambda (self value)
     (string-upcase
      (gen-c-symbol (string-append (obj:str-name self)
  "_"
! (symbol->string value)))))
  )
 
  ; Called before loading a .cpu file to initialize.
--- 961,1042 ----
  )
 
  (method-make!
+  <boolean-attribute> 'gen-value-for-defn
+  (lambda (self value)
+    (send self 'gen-value-for-defn-raw value))
+ )
+
+ (method-make!
+  <bitset-attribute> 'gen-value-for-defn-raw
+  (lambda (self value)
+    (if (string=? (string-downcase (gen-sym self)) "isa")
+        (bitset-attr->charmask value (elm-get self 'values))
+        (string-drop1
+ (string-upcase
+ (string-map (lambda (x)
+       (string-append "|(1<<"
+      (gen-sym self)
+      "_" (gen-c-symbol x) ")"))
+     (bitset-attr->list value)))))
+  )
+ )
+
+ (method-make!
   <bitset-attribute> 'gen-value-for-defn
   (lambda (self value)
!    (string-append
!     "{ "
!     (if (string=? (string-downcase (gen-sym self)) "isa")
! (bitset-attr->charmask value (elm-get self 'values))
! (string-append
! "{ "
! (string-drop1
!  (string-upcase
!   (string-map (lambda (x)
! (string-append "|(1<<"
! (gen-sym self)
! "_" (gen-c-symbol x) ")"))
!       (bitset-attr->list value))))
! ", 0 }"))
!     " }")
!  )
! )
!
! (method-make!
!  <integer-attribute> 'gen-value-for-defn-raw
!  (lambda (self value)
!    (number->string value)
!  )
  )
 
  (method-make!
   <integer-attribute> 'gen-value-for-defn
   (lambda (self value)
!    (string-append
!     "{ { "
!     (send self 'gen-value-for-defn-raw value)
!     ", 0 } }")
!  )
  )
 
  (method-make!
!  <enum-attribute> 'gen-value-for-defn-raw
   (lambda (self value)
     (string-upcase
      (gen-c-symbol (string-append (obj:str-name self)
  "_"
! (symbol->string value))))
!  )
! )
!
! (method-make!
!  <enum-attribute> 'gen-value-for-defn
!  (lambda (self value)
!    (string-append
!     "{ { "
!      (send self 'gen-value-for-defn-raw value)
!      ", 0 } }")
!  )
  )
 
  ; Called before loading a .cpu file to initialize.
Index: cgen/desc-cpu.scm
===================================================================
RCS file: /cvs/src/src/cgen/desc-cpu.scm,v
retrieving revision 1.21
diff -c -p -r1.21 desc-cpu.scm
*** cgen/desc-cpu.scm 1 Jul 2005 11:16:30 -0000 1.21
--- cgen/desc-cpu.scm 19 Sep 2005 19:48:42 -0000
*************** static const CGEN_MACH @arch@_cgen_mach_
*** 114,119 ****
--- 114,120 ----
     "/* Ifield support.  */\n\n"
     "/* Ifield attribute indices.  */\n\n"
     (gen-attr-enum-decl "cgen_ifld" (current-ifld-attr-list))
+    (-gen-attr-accessors "cgen_ifld" (current-ifld-attr-list))
     (gen-enum-decl 'ifield_type "@arch@ ifield types"
   "@ARCH@_"
   (append (gen-obj-list-enums (non-derived-ifields (current-ifld-list)))
*************** const CGEN_IFLD @arch@_cgen_ifld_table[]
*** 161,167 ****
    "  },\n")))
        ifld-list)
       "\
!   { 0, 0, 0, 0, 0, 0, {0, {0}} }
  };
 
  #undef A
--- 162,168 ----
    "  },\n")))
        ifld-list)
       "\
!   { 0, 0, 0, 0, 0, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
  };
 
  #undef A
*************** const CGEN_IFLD @arch@_cgen_ifld_table[]
*** 180,185 ****
--- 181,187 ----
    (string-list
     "/* Hardware attribute indices.  */\n\n"
     (gen-attr-enum-decl "cgen_hw" (current-hw-attr-list))
+    (-gen-attr-accessors "cgen_hw" (current-hw-attr-list))
     (gen-enum-decl 'cgen_hw_type "@arch@ hardware types"
   "HW_" ; FIXME: @ARCH@_
   (append (nub (map (lambda (hw)
*************** const CGEN_HW_ENTRY @arch@_cgen_hw_table
*** 281,287 ****
    " },\n")))
        (current-hw-list))
       "\
!   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
  };
 
  #undef A
--- 283,289 ----
    " },\n")))
        (current-hw-list))
       "\
!   { 0, 0, CGEN_ASM_NONE, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
  };
 
  #undef A
*************** const CGEN_HW_ENTRY @arch@_cgen_hw_table
*** 298,303 ****
--- 300,307 ----
  (define (-gen-hash-defines)
    (logit 2 "Generating #define's ...\n")
    (string-list
+    "#include \"opcode/cgen-bitset.h\"\n"
+    "\n"
     "#define CGEN_ARCH @arch@\n\n"
     "/* Given symbol S, return @arch@_cgen_<S>.  */\n"
     (gen-define-with-symcat "CGEN_SYM(s) @arch@" "_cgen_" "s")
*************** const CGEN_HW_ENTRY @arch@_cgen_hw_table
*** 365,370 ****
--- 369,375 ----
    (string-list
     "/* Operand attribute indices.  */\n\n"
     (gen-attr-enum-decl "cgen_operand" (current-op-attr-list))
+    (-gen-attr-accessors "cgen_operand" (current-op-attr-list))
     (gen-enum-decl 'cgen_operand_type "@arch@ operand types"
   "@ARCH@_OPERAND_"
   (nub (append (gen-obj-list-enums (current-op-list))
*************** const CGEN_OPERAND @arch@_cgen_operand_t
*** 475,481 ****
       )))))
        (current-op-list))
       "/* sentinel */\n\
!   { 0, 0, 0, 0, 0,\n    { 0, { (const PTR) 0 } },\n    { 0, { 0 } } }
  };
 
  #undef A
--- 480,486 ----
       )))))
        (current-op-list))
       "/* sentinel */\n\
!   { 0, 0, 0, 0, 0,\n    { 0, { (const PTR) 0 } },\n    " (gen-obj-attr-end-defn all-attrs num-non-bools) " }
  };
 
  #undef A
*************** const CGEN_OPERAND @arch@_cgen_operand_t
*** 494,499 ****
--- 499,505 ----
    (string-list
     "/* Insn attribute indices.  */\n\n"
     (gen-attr-enum-decl "cgen_insn" (current-insn-attr-list))
+    (-gen-attr-accessors "cgen_insn" (current-insn-attr-list))
     )
  )
 
*************** static const CGEN_IBASE @arch@_cgen_insn
*** 552,558 ****
    /* Special null first entry.
       A `num' value of zero is thus invalid.
       Also, the special `invalid' insn resides here.  */
!   { 0, 0, 0, 0, {0, {0}} },\n"
 
       (lambda ()
         (string-write-map (lambda (insn)
--- 558,564 ----
    /* Special null first entry.
       A `num' value of zero is thus invalid.
       Also, the special `invalid' insn resides here.  */
!   { 0, 0, 0, 0, " (gen-obj-attr-end-defn all-attrs num-non-bools) " },\n"
 
       (lambda ()
         (string-write-map (lambda (insn)
*************** static void
*** 696,702 ****
  @arch@_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
  {
    int i;
!   unsigned int isas = cd->isas;
    unsigned int machs = cd->machs;
 
    cd->int_insn_p = CGEN_INT_INSN_P;
--- 702,708 ----
  @arch@_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
  {
    int i;
!   CGEN_BITSET *isas = cd->isas;
    unsigned int machs = cd->machs;
 
    cd->int_insn_p = CGEN_INT_INSN_P;
*************** static void
*** 708,714 ****
    cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
    cd->max_insn_bitsize = 0;
    for (i = 0; i < MAX_ISAS; ++i)
!     if (((1 << i) & isas) != 0)
        {
  const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
 
--- 714,720 ----
    cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
    cd->max_insn_bitsize = 0;
    for (i = 0; i < MAX_ISAS; ++i)
!     if (cgen_bitset_contains (isas, i))
        {
  const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
 
*************** CGEN_CPU_DESC
*** 793,799 ****
  {
    CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
    static int init_p;
!   unsigned int isas = 0;  /* 0 = \"unspecified\" */
    unsigned int machs = 0; /* 0 = \"unspecified\" */
    enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
    va_list ap;
--- 799,805 ----
  {
    CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
    static int init_p;
!   CGEN_BITSET *isas = 0;  /* 0 = \"unspecified\" */
    unsigned int machs = 0; /* 0 = \"unspecified\" */
    enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
    va_list ap;
*************** CGEN_CPU_DESC
*** 812,818 ****
        switch (arg_type)
  {
  case CGEN_CPU_OPEN_ISAS :
!  isas = va_arg (ap, unsigned int);
   break;
  case CGEN_CPU_OPEN_MACHS :
   machs = va_arg (ap, unsigned int);
--- 818,824 ----
        switch (arg_type)
  {
  case CGEN_CPU_OPEN_ISAS :
!  isas = va_arg (ap, CGEN_BITSET *);
   break;
  case CGEN_CPU_OPEN_MACHS :
   machs = va_arg (ap, unsigned int);
*************** CGEN_CPU_DESC
*** 843,851 ****
      machs = (1 << MAX_MACHS) - 1;
    /* Base mach is always selected.  */
    machs |= 1;
-   /* ISA unspecified means \"all\".  */
-   if (isas == 0)
-     isas = (1 << MAX_ISAS) - 1;
    if (endian == CGEN_ENDIAN_UNKNOWN)
      {
        /* ??? If target has only one, could have a default.  */
--- 849,854 ----
*************** CGEN_CPU_DESC
*** 853,859 ****
        abort ();
      }
 
!   cd->isas = isas;
    cd->machs = machs;
    cd->endian = endian;
    /* FIXME: for the sparc case we can determine insn-endianness statically.
--- 856,862 ----
        abort ();
      }
 
!   cd->isas = cgen_bitset_copy (isas);
    cd->machs = machs;
    cd->endian = endian;
    /* FIXME: for the sparc case we can determine insn-endianness statically.
Index: cgen/desc.scm
===================================================================
RCS file: /cvs/src/src/cgen/desc.scm,v
retrieving revision 1.4
diff -c -p -r1.4 desc.scm
*** cgen/desc.scm 16 Jul 2003 05:35:47 -0000 1.4
--- cgen/desc.scm 19 Sep 2005 19:48:42 -0000
***************
*** 1,5 ****
  ; General cpu info generator support.
! ; Copyright (C) 2000 Red Hat, Inc.
  ; This file is part of CGEN.
  ;
  ; This file generates C versions of the more salient parts of the description
--- 1,5 ----
  ; General cpu info generator support.
! ; Copyright (C) 2000, 2003 Red Hat, Inc.
  ; This file is part of CGEN.
  ;
  ; This file generates C versions of the more salient parts of the description
*************** static const CGEN_ATTR_ENTRY bool_attr[]
*** 128,134 ****
  (if (string? (cadr e))
     (cadr e)
     (number->string (cadr e))) ; value
! ", {0, {0}}, 0, 0"
  " },\n"
  ))
      (elm-get self 'values)))
--- 128,134 ----
  (if (string? (cadr e))
     (cadr e)
     (number->string (cadr e))) ; value
! ", {0, {{{0, 0}}}}, 0, 0"
  " },\n"
  ))
      (elm-get self 'values)))
Index: cgen/mach.scm
===================================================================
RCS file: /cvs/src/src/cgen/mach.scm,v
retrieving revision 1.9
diff -c -p -r1.9 mach.scm
*** cgen/mach.scm 15 Jun 2005 21:28:18 -0000 1.9
--- cgen/mach.scm 19 Sep 2005 19:48:42 -0000
***************
*** 1,5 ****
  ; CPU architecture description.
! ; Copyright (C) 2000 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
--- 1,5 ----
  ; CPU architecture description.
! ; Copyright (C) 2000, 2003 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
 
***************
*** 902,909 ****
    (apply min (cons 65535
    (map insn-length (find (lambda (insn)
     (and (not (has-attr? insn 'ALIAS))
! (eq? (obj-attr-value insn 'ISA)
!      (obj:name isa))))
   (non-multi-insns (current-insn-list))))))
  )
 
--- 902,908 ----
    (apply min (cons 65535
    (map insn-length (find (lambda (insn)
     (and (not (has-attr? insn 'ALIAS))
! (isa-supports? isa insn)))
   (non-multi-insns (current-insn-list))))))
  )
 
***************
*** 913,920 ****
    (apply max (cons 0
    (map insn-length (find (lambda (insn)
     (and (not (has-attr? insn 'ALIAS))
! (eq? (obj-attr-value insn 'ISA)
!      (obj:name isa))))
   (non-multi-insns (current-insn-list))))))
  )
 
--- 912,918 ----
    (apply max (cons 0
    (map insn-length (find (lambda (insn)
     (and (not (has-attr? insn 'ALIAS))
! (isa-supports? isa insn)))
   (non-multi-insns (current-insn-list))))))
  )
 
Index: cgen/sid-cpu.scm
===================================================================
RCS file: /cvs/src/src/cgen/sid-cpu.scm,v
retrieving revision 1.13
diff -c -p -r1.13 sid-cpu.scm
*** cgen/sid-cpu.scm 29 Jul 2005 19:25:33 -0000 1.13
--- cgen/sid-cpu.scm 19 Sep 2005 19:48:42 -0000
***************
*** 80,85 ****
--- 80,87 ----
  #ifndef DESC_@ARCH@_H
  #define DESC_@ARCH@_H
 
+ #include \"opcode/cgen-bitset.h\"
+
  namespace @arch@ {
  \n"
 
*************** using namespace cgen;
*** 650,660 ****
     "_memory")
      m 1))
  modes)))
-
      (logit 2 "Generating writer function ...\n")
      (string-append
       "
-
    void @prefix@::write_stacks::writeback (int tick, @cpu@::@cpu@_cpu* current_cpu)
    {
  "
--- 652,660 ----
Index: cgen/sid.scm
===================================================================
RCS file: /cvs/src/src/cgen/sid.scm,v
retrieving revision 1.15
diff -c -p -r1.15 sid.scm
*** cgen/sid.scm 15 Jun 2005 21:28:19 -0000 1.15
--- cgen/sid.scm 19 Sep 2005 19:48:42 -0000
***************
*** 230,236 ****
        (attr-default attr))))
   ; FIXME: Are we missing attr-prefix here?
   (string-append ", "
! (send attr 'gen-value-for-defn val))))
       all-non-bools)))
       " }"))
  )
--- 230,236 ----
        (attr-default attr))))
   ; FIXME: Are we missing attr-prefix here?
   (string-append ", "
! (send attr 'gen-value-for-defn-raw val))))
       all-non-bools)))
       " }"))
  )
Index: cgen/utils-cgen.scm
===================================================================
RCS file: /cvs/src/src/cgen/utils-cgen.scm,v
retrieving revision 1.6
diff -c -p -r1.6 utils-cgen.scm
*** cgen/utils-cgen.scm 16 Dec 2004 21:24:07 -0000 1.6
--- cgen/utils-cgen.scm 19 Sep 2005 19:48:42 -0000
***************
*** 1,5 ****
  ; CGEN Utilities.
! ; Copyright (C) 2000 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
  ;
--- 1,5 ----
  ; CGEN Utilities.
! ; Copyright (C) 2000, 2002, 2003 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
  ;
***************
*** 467,472 ****
--- 467,530 ----
 
  ; Attributes
 
+ ; Return the C/C++ type to use to hold a value for attribute ATTR.
+
+ (define (gen-attr-type attr)
+   (if (string=? (string-downcase (gen-sym attr)) "isa")
+       "CGEN_BITSET"
+       (case (attr-kind attr)
+ ((boolean) "int")
+ ((bitset)  "unsigned int")
+ ((integer) "int")
+ ((enum)    (string-append "enum " (string-downcase (gen-sym attr)) "_attr"))
+ ))
+ )
+
+ ; Return C macros for accessing an object's attributes ATTRS.
+ ; PREFIX is one of "cgen_ifld", "cgen_hw", "cgen_operand", "cgen_insn".
+ ; ATTRS is an alist of attribute values.  The value is unimportant except that
+ ; it is used to determine bool/non-bool.
+ ; Non-bools need to be separated from bools as they're each recorded
+ ; differently.  Non-bools are recorded in an int for each.  All bools are
+ ; combined into one int to save space.
+ ; ??? We assume there is at least one bool.
+
+ (define (-gen-attr-accessors prefix attrs)
+   (string-append
+    "/* " prefix " attribute accessor macros.  */\n"
+    (string-map (lambda (attr)
+ (string-append
+  "#define CGEN_ATTR_"
+  (string-upcase prefix)
+  "_"
+  (string-upcase (gen-sym attr))
+  "_VALUE(attrs) "
+  (if (bool-attr? attr)
+      (string-append
+       "(((attrs)->bool & (1 << "
+       (string-upcase prefix)
+       "_"
+       (string-upcase (gen-sym attr))
+       ")) != 0)")
+      (string-append
+       "((attrs)->nonbool["
+       (string-upcase prefix)
+       "_"
+       (string-upcase (gen-sym attr))
+       "-"
+       (string-upcase prefix)
+       "_START_NBOOLS-1]."
+       (case (attr-kind attr)
+ ((bitset)
+  (if (string=? (string-downcase (gen-sym attr)) "isa")
+      ""
+      "non"))
+ (else "non"))
+       "bitset)"))
+  "\n"))
+       attrs)
+    "\n")
+ )
  ; Return C code to declare an enum of attributes ATTRS.
  ; PREFIX is one of "cgen_ifld", "cgen_hw", "cgen_operand", "cgen_insn".
  ; ATTRS is an alist of attribute values.  The value is unimportant except that
***************
*** 565,570 ****
--- 623,649 ----
     ))
  )
 
+ ; Return the C definition of the terminating entry of an object's attributes.
+ ; ALL-ATTRS is an ordered alist of all attributes.
+ ; "ordered" means all the non-boolean attributes are at the front and
+ ; duplicate entries have been removed.
+
+ (define (gen-obj-attr-end-defn all-attrs num-non-bools)
+   (let ((all-non-bools (list-take num-non-bools all-attrs)))
+     (string-append
+      "{ 0, {"
+      (if (null? all-non-bools)
+ " { 0, 0 }"
+ (string-drop1 ; drop the leading ","
+  (string-map (lambda (attr)
+ (let ((val (attr-default attr)))
+ ; FIXME: Are we missing attr-prefix here?
+  (string-append ", "
+ (send attr 'gen-value-for-defn val))))
+      all-non-bools)))
+      " } }"
+      ))
+ )
  ; Return a boolean indicating if ATLIST indicates a CTI insn.
 
  (define (atlist-cti? atlist)
Index: cpu/frv.opc
===================================================================
RCS file: /cvs/src/src/cpu/frv.opc,v
retrieving revision 1.13
diff -c -p -r1.13 frv.opc
*** cpu/frv.opc 1 Jul 2005 11:16:30 -0000 1.13
--- cpu/frv.opc 19 Sep 2005 19:48:42 -0000
***************
*** 50,56 ****
  #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8.  */
  #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
 
! typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
 
  typedef struct
  {
--- 50,56 ----
  #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8.  */
  #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL
 
! typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE];
 
  typedef struct
  {
*************** typedef struct
*** 58,72 ****
    int                    constraint_violation;
    unsigned long          mach;
    unsigned long          elf_flags;
!   CGEN_ATTR_VALUE_TYPE * unit_mapping;
    VLIW_COMBO *           current_vliw;
!   CGEN_ATTR_VALUE_TYPE   major[FRV_VLIW_SIZE];
    const CGEN_INSN *      insn[FRV_VLIW_SIZE];
  } FRV_VLIW;
 
! int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long);
! int frv_is_float_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
! int frv_is_media_major  (CGEN_ATTR_VALUE_TYPE, unsigned long);
  int frv_is_branch_insn  (const CGEN_INSN *);
  int frv_is_float_insn   (const CGEN_INSN *);
  int frv_is_media_insn   (const CGEN_INSN *);
--- 58,72 ----
    int                    constraint_violation;
    unsigned long          mach;
    unsigned long          elf_flags;
!   CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping;
    VLIW_COMBO *           current_vliw;
!   CGEN_ATTR_VALUE_ENUM_TYPE   major[FRV_VLIW_SIZE];
    const CGEN_INSN *      insn[FRV_VLIW_SIZE];
  } FRV_VLIW;
 
! int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
! int frv_is_float_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
! int frv_is_media_major  (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long);
  int frv_is_branch_insn  (const CGEN_INSN *);
  int frv_is_float_insn   (const CGEN_INSN *);
  int frv_is_media_insn   (const CGEN_INSN *);
*************** int spr_valid           (long);
*** 83,89 ****
     development tree.  */
 
  bfd_boolean
! frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
  {
    switch (mach)
      {
--- 83,89 ----
     development tree.  */
 
  bfd_boolean
! frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
  {
    switch (mach)
      {
*************** frv_is_branch_major (CGEN_ATTR_VALUE_TYP
*** 107,113 ****
  /* Returns TRUE if {MAJOR,MACH} supports floating point insns.  */
 
  bfd_boolean
! frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
  {
    switch (mach)
      {
--- 107,113 ----
  /* Returns TRUE if {MAJOR,MACH} supports floating point insns.  */
 
  bfd_boolean
! frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
  {
    switch (mach)
      {
*************** frv_is_float_major (CGEN_ATTR_VALUE_TYPE
*** 126,132 ****
  /* Returns TRUE if {MAJOR,MACH} supports media insns.  */
 
  bfd_boolean
! frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
  {
    switch (mach)
      {
--- 126,132 ----
  /* Returns TRUE if {MAJOR,MACH} supports media insns.  */
 
  bfd_boolean
! frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach)
  {
    switch (mach)
      {
*************** static VLIW_COMBO fr550_allowed_vliw[] =
*** 270,276 ****
  /* Some insns are assigned specialized implementation units which map to
     different actual implementation units on different machines.  These
     tables perform that mapping.  */
! static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
--- 270,276 ----
  /* Some insns are assigned specialized implementation units which map to
     different actual implementation units on different machines.  These
     tables perform that mapping.  */
! static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
*************** static CGEN_ATTR_VALUE_TYPE fr400_unit_m
*** 305,311 ****
  /* Some insns are assigned specialized implementation units which map to
     different actual implementation units on different machines.  These
     tables perform that mapping.  */
! static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
--- 305,311 ----
  /* Some insns are assigned specialized implementation units which map to
     different actual implementation units on different machines.  These
     tables perform that mapping.  */
! static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
*************** static CGEN_ATTR_VALUE_TYPE fr450_unit_m
*** 337,343 ****
  /* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
  };
 
! static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
--- 337,343 ----
  /* MCLRACC-1*/     UNIT_FM0  /* mclracc,A==1   insn only in FM0 unit.  */
  };
 
! static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
*************** static CGEN_ATTR_VALUE_TYPE fr500_unit_m
*** 369,375 ****
  /* MCLRACC-1*/     UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit.  */
  };
 
! static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
--- 369,375 ----
  /* MCLRACC-1*/     UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit.  */
  };
 
! static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] =
  {
  /* unit in insn    actual unit */
  /* NIL      */     UNIT_NIL,
*************** frv_vliw_reset (FRV_VLIW *vliw, unsigned
*** 435,441 ****
     *_allowed_vliw tables above.  */
  static bfd_boolean
  match_unit (FRV_VLIW *vliw,
!    CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2)
  {
    /* Map any specialized implementation units to actual ones.  */
    unit1 = vliw->unit_mapping[unit1];
--- 435,441 ----
     *_allowed_vliw tables above.  */
  static bfd_boolean
  match_unit (FRV_VLIW *vliw,
!    CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2)
  {
    /* Map any specialized implementation units to actual ones.  */
    unit1 = vliw->unit_mapping[unit1];
*************** match_vliw (VLIW_COMBO *vliw1, VLIW_COMB
*** 487,493 ****
     If one is found then return it. Otherwise return NULL.  */
 
  static VLIW_COMBO *
! add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
  {
    int           next    = vliw->next_slot;
    VLIW_COMBO    *current = vliw->current_vliw;
--- 487,493 ----
     If one is found then return it. Otherwise return NULL.  */
 
  static VLIW_COMBO *
! add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
  {
    int           next    = vliw->next_slot;
    VLIW_COMBO    *current = vliw->current_vliw;
*************** add_next_to_vliw (FRV_VLIW *vliw, CGEN_A
*** 518,524 ****
     Returns TRUE if found, FALSE otherwise.  */
 
  static bfd_boolean
! find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
  {
    int i;
 
--- 518,524 ----
     Returns TRUE if found, FALSE otherwise.  */
 
  static bfd_boolean
! find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
  {
    int i;
 
*************** find_major_in_vliw (FRV_VLIW *vliw, CGEN
*** 533,539 ****
     types.  */
 
  static bfd_boolean
! fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
  {
    /* In the cpu file, all media insns are represented as being allowed in
       both media units. This makes it easier since this is the case for fr500.
--- 533,539 ----
     types.  */
 
  static bfd_boolean
! fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
  {
    /* In the cpu file, all media insns are represented as being allowed in
       both media units. This makes it easier since this is the case for fr500.
*************** fr400_check_insn_major_constraints (FRV_
*** 553,561 ****
  }
 
  static bfd_boolean
! fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
  {
!   CGEN_ATTR_VALUE_TYPE other_major;
 
    /* Our caller guarantees there's at least one other instruction.  */
    other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
--- 553,561 ----
  }
 
  static bfd_boolean
! fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
  {
!   CGEN_ATTR_VALUE_ENUM_TYPE other_major;
 
    /* Our caller guarantees there's at least one other instruction.  */
    other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
*************** fr450_check_insn_major_constraints (FRV_
*** 588,594 ****
  }
 
  static bfd_boolean
! find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit)
  {
    int i;
 
--- 588,594 ----
  }
 
  static bfd_boolean
! find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit)
  {
    int i;
 
*************** find_unit_in_vliw (FRV_VLIW *vliw, CGEN_
*** 601,608 ****
 
  static bfd_boolean
  find_major_in_slot (FRV_VLIW *vliw,
!    CGEN_ATTR_VALUE_TYPE major,
!    CGEN_ATTR_VALUE_TYPE slot)
  {
    int i;
 
--- 601,608 ----
 
  static bfd_boolean
  find_major_in_slot (FRV_VLIW *vliw,
!    CGEN_ATTR_VALUE_ENUM_TYPE major,
!    CGEN_ATTR_VALUE_ENUM_TYPE slot)
  {
    int i;
 
*************** fr550_find_float_in_vliw (FRV_VLIW *vliw
*** 657,667 ****
 
  static bfd_boolean
  fr550_check_insn_major_constraints (FRV_VLIW *vliw,
!    CGEN_ATTR_VALUE_TYPE major,
     const CGEN_INSN *insn)
  {
!   CGEN_ATTR_VALUE_TYPE unit;
!   CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
    switch (slot)
      {
      case UNIT_I2:
--- 657,667 ----
 
  static bfd_boolean
  fr550_check_insn_major_constraints (FRV_VLIW *vliw,
!    CGEN_ATTR_VALUE_ENUM_TYPE major,
     const CGEN_INSN *insn)
  {
!   CGEN_ATTR_VALUE_ENUM_TYPE unit;
!   CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot];
    switch (slot)
      {
      case UNIT_I2:
*************** fr550_check_insn_major_constraints (FRV_
*** 707,713 ****
  }
 
  static bfd_boolean
! fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major)
  {
    /* TODO: A table might be faster for some of the more complex instances
       here.  */
--- 707,713 ----
  }
 
  static bfd_boolean
! fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major)
  {
    /* TODO: A table might be faster for some of the more complex instances
       here.  */
*************** fr500_check_insn_major_constraints (FRV_
*** 815,821 ****
 
  static bfd_boolean
  check_insn_major_constraints (FRV_VLIW *vliw,
!      CGEN_ATTR_VALUE_TYPE major,
       const CGEN_INSN *insn)
  {
    switch (vliw->mach)
--- 815,821 ----
 
  static bfd_boolean
  check_insn_major_constraints (FRV_VLIW *vliw,
!      CGEN_ATTR_VALUE_ENUM_TYPE major,
       const CGEN_INSN *insn)
  {
    switch (vliw->mach)
*************** int
*** 841,848 ****
  frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
  {
    int index;
!   CGEN_ATTR_VALUE_TYPE major;
!   CGEN_ATTR_VALUE_TYPE unit;
    VLIW_COMBO *new_vliw;
 
    if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
--- 841,848 ----
  frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
  {
    int index;
!   CGEN_ATTR_VALUE_ENUM_TYPE major;
!   CGEN_ATTR_VALUE_ENUM_TYPE unit;
    VLIW_COMBO *new_vliw;
 
    if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn))
Index: cpu/m32c.opc
===================================================================
RCS file: /cvs/src/src/cpu/m32c.opc,v
retrieving revision 1.5
diff -c -p -r1.5 m32c.opc
*** cpu/m32c.opc 26 Jul 2005 03:21:50 -0000 1.5
--- cpu/m32c.opc 19 Sep 2005 19:48:42 -0000
*************** m32c_cgen_insn_supported (CGEN_CPU_DESC
*** 775,788 ****
   const CGEN_INSN *insn)
  {
    int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
!   int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA);
 
    /* If attributes are absent, assume no restriction.  */
    if (machs == 0)
      machs = ~0;
 
    return ((machs & cd->machs)
!  && (isas & cd->isas));
  }
 
  /* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */
--- 775,788 ----
   const CGEN_INSN *insn)
  {
    int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH);
!   CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA);
 
    /* If attributes are absent, assume no restriction.  */
    if (machs == 0)
      machs = ~0;
 
    return ((machs & cd->machs)
!           && cgen_bitset_intersect_p (& isas, cd->isas));
  }
 
  /* Parse a set of registers, R0,R1,A0,A1,SB,FB.  */
Index: gas/config/tc-m32c.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-m32c.c,v
retrieving revision 1.3
diff -c -p -r1.3 tc-m32c.c
*** gas/config/tc-m32c.c 26 Jul 2005 03:21:52 -0000 1.3
--- gas/config/tc-m32c.c 19 Sep 2005 19:48:44 -0000
*************** static int insn_size;
*** 87,98 ****
  /* Flags to set in the elf header */
  static flagword m32c_flags = DEFAULT_FLAGS;
 
! static unsigned int m32c_isa = (1 << ISA_M16C);
 
  static void
  set_isa (enum isa_attr isa_num)
  {
!   m32c_isa = (1 << isa_num);
  }
 
  static void s_bss (int);
--- 87,99 ----
  /* Flags to set in the elf header */
  static flagword m32c_flags = DEFAULT_FLAGS;
 
! static char default_isa = 1 << (7 - ISA_M16C);
! static CGEN_BITSET m32c_isa = {1, & default_isa};
 
  static void
  set_isa (enum isa_attr isa_num)
  {
!   cgen_bitset_set (& m32c_isa, isa_num);
  }
 
  static void s_bss (int);
*************** md_begin (void)
*** 156,162 ****
    gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
   CGEN_CPU_OPEN_ENDIAN,
   CGEN_ENDIAN_BIG,
!  CGEN_CPU_OPEN_ISAS, m32c_isa,
   CGEN_CPU_OPEN_END);
 
    m32c_cgen_init_asm (gas_cgen_cpu_desc);
--- 157,163 ----
    gas_cgen_cpu_desc = m32c_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, cpu_mach,
   CGEN_CPU_OPEN_ENDIAN,
   CGEN_ENDIAN_BIG,
!  CGEN_CPU_OPEN_ISAS, & m32c_isa,
   CGEN_CPU_OPEN_END);
 
    m32c_cgen_init_asm (gas_cgen_cpu_desc);
Index: include/dis-asm.h
===================================================================
RCS file: /cvs/src/src/include/dis-asm.h,v
retrieving revision 1.56
diff -c -p -r1.56 dis-asm.h
*** include/dis-asm.h 18 Aug 2005 03:49:39 -0000 1.56
--- include/dis-asm.h 19 Sep 2005 19:48:49 -0000
*************** typedef struct disassemble_info {
*** 78,84 ****
       for processors with run-time-switchable instruction sets.  The default,
       zero, means that there is no constraint.  CGEN-based opcodes ports
       may use ISA_foo masks.  */
!   unsigned long insn_sets;
 
    /* Some targets need information about the current section to accurately
       display insns.  If this is NULL, the target disassembler function
--- 78,84 ----
       for processors with run-time-switchable instruction sets.  The default,
       zero, means that there is no constraint.  CGEN-based opcodes ports
       may use ISA_foo masks.  */
!   void *insn_sets;
 
    /* Some targets need information about the current section to accurately
       display insns.  If this is NULL, the target disassembler function
Index: include/opcode/cgen.h
===================================================================
RCS file: /cvs/src/src/include/opcode/cgen.h,v
retrieving revision 1.22
diff -c -p -r1.22 cgen.h
*** include/opcode/cgen.h 10 May 2005 10:21:12 -0000 1.22
--- include/opcode/cgen.h 19 Sep 2005 19:48:51 -0000
*************** with this program; if not, write to the
*** 22,27 ****
--- 22,29 ----
  #ifndef CGEN_H
  #define CGEN_H
 
+ #include "symcat.h"
+ #include "cgen-bitset.h"
  /* ??? This file requires bfd.h but only to get bfd_vma.
     Seems like an awful lot to require just to get such a fundamental type.
     Perhaps the definition of bfd_vma can be moved outside of bfd.h.
*************** typedef struct cgen_cpu_desc *CGEN_CPU_D
*** 107,113 ****
 
  /* Type of attribute values.  */
 
! typedef int CGEN_ATTR_VALUE_TYPE;
 
  /* Struct to record attribute information.  */
 
--- 109,121 ----
 
  /* Type of attribute values.  */
 
! typedef CGEN_BITSET     CGEN_ATTR_VALUE_BITSET_TYPE;
! typedef int             CGEN_ATTR_VALUE_ENUM_TYPE;
! typedef union
! {
!   CGEN_ATTR_VALUE_BITSET_TYPE bitset;
!   CGEN_ATTR_VALUE_ENUM_TYPE   nonbitset;
! } CGEN_ATTR_VALUE_TYPE;
 
  /* Struct to record attribute information.  */
 
*************** struct { unsigned int bool; \
*** 153,159 ****
  #define CGEN_ATTR_VALUE(obj, attr_table, attr) \
  ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
   ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
!  : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET]))
 
  /* Attribute name/value tables.
     These are used to assist parsing of descriptions at run-time.  */
--- 161,169 ----
  #define CGEN_ATTR_VALUE(obj, attr_table, attr) \
  ((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \
   ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \
!  : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset))
! #define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \
!  ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset)
 
  /* Attribute name/value tables.
     These are used to assist parsing of descriptions at run-time.  */
*************** struct { unsigned int bool; \
*** 161,167 ****
  typedef struct
  {
    const char * name;
!   CGEN_ATTR_VALUE_TYPE value;
  } CGEN_ATTR_ENTRY;
 
  /* For each domain (ifld,hw,operand,insn), list of attributes.  */
--- 171,177 ----
  typedef struct
  {
    const char * name;
!   unsigned value;
  } CGEN_ATTR_ENTRY;
 
  /* For each domain (ifld,hw,operand,insn), list of attributes.  */
*************** typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_
*** 965,970 ****
--- 975,981 ----
  typedef enum cgen_insn_attr {
    CGEN_INSN_ALIAS = 0
  } CGEN_INSN_ATTR;
+ #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS))
  #endif
 
  /* This struct defines each entry in the instruction table.  */
*************** typedef struct
*** 1016,1021 ****
--- 1027,1034 ----
  /* Return value of attribute ATTR in INSN.  */
  #define CGEN_INSN_ATTR_VALUE(insn, attr) \
  CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
+ #define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \
+   CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
  } CGEN_IBASE;
 
  /* Return non-zero if INSN is the "invalid" insn marker.  */
*************** typedef struct cgen_cpu_desc
*** 1179,1188 ****
    /* Bitmap of selected machine(s) (a la BFD machine number).  */
    int machs;
 
!   /* Bitmap of selected isa(s).
!      ??? Simultaneous multiple isas might not make sense, but it's not (yet)
!      precluded.  */
!   int isas;
 
    /* Current endian.  */
    enum cgen_endian endian;
--- 1192,1200 ----
    /* Bitmap of selected machine(s) (a la BFD machine number).  */
    int machs;
 
!   /* Bitmap of selected isa(s).  */
!   CGEN_BITSET *isas;
! #define CGEN_CPU_ISAS(cd) ((cd)->isas)
 
    /* Current endian.  */
    enum cgen_endian endian;
Index: opcodes/cgen-dis.in
===================================================================
RCS file: /cvs/src/src/opcodes/cgen-dis.in,v
retrieving revision 1.21
diff -c -p -r1.21 cgen-dis.in
*** opcodes/cgen-dis.in 1 Jul 2005 11:16:31 -0000 1.21
--- opcodes/cgen-dis.in 19 Sep 2005 19:48:54 -0000
***************
*** 4,10 ****
     THIS FILE IS MACHINE GENERATED WITH CGEN.
     - the resultant file is machine generated, cgen-dis.in isn't
 
!    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
     Free Software Foundation, Inc.
 
     This file is part of the GNU Binutils and GDB, the GNU debugger.
--- 4,10 ----
     THIS FILE IS MACHINE GENERATED WITH CGEN.
     - the resultant file is machine generated, cgen-dis.in isn't
 
!    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
     Free Software Foundation, Inc.
 
     This file is part of the GNU Binutils and GDB, the GNU debugger.
*************** default_print_insn (CGEN_CPU_DESC cd, bf
*** 347,353 ****
  typedef struct cpu_desc_list
  {
    struct cpu_desc_list *next;
!   int isa;
    int mach;
    int endian;
    CGEN_CPU_DESC cd;
--- 347,353 ----
  typedef struct cpu_desc_list
  {
    struct cpu_desc_list *next;
!   CGEN_BITSET *isa;
    int mach;
    int endian;
    CGEN_CPU_DESC cd;
*************** print_insn_@arch@ (bfd_vma pc, disassemb
*** 359,369 ****
    static cpu_desc_list *cd_list = 0;
    cpu_desc_list *cl = 0;
    static CGEN_CPU_DESC cd = 0;
!   static int prev_isa;
    static int prev_mach;
    static int prev_endian;
    int length;
!   int isa,mach;
    int endian = (info->endian == BFD_ENDIAN_BIG
  ? CGEN_ENDIAN_BIG
  : CGEN_ENDIAN_LITTLE);
--- 359,370 ----
    static cpu_desc_list *cd_list = 0;
    cpu_desc_list *cl = 0;
    static CGEN_CPU_DESC cd = 0;
!   static CGEN_BITSET *prev_isa;
    static int prev_mach;
    static int prev_endian;
    int length;
!   CGEN_BITSET *isa;
!   int mach;
    int endian = (info->endian == BFD_ENDIAN_BIG
  ? CGEN_ENDIAN_BIG
  : CGEN_ENDIAN_LITTLE);
*************** print_insn_@arch@ (bfd_vma pc, disassemb
*** 386,410 ****
  #endif
 
  #ifdef CGEN_COMPUTE_ISA
!   isa = CGEN_COMPUTE_ISA (info);
  #else
    isa = info->insn_sets;
  #endif
 
    /* If we've switched cpu's, try to find a handle we've used before */
    if (cd
!       && (isa != prev_isa
   || mach != prev_mach
   || endian != prev_endian))
      {
        cd = 0;
        for (cl = cd_list; cl; cl = cl->next)
  {
!  if (cl->isa == isa &&
       cl->mach == mach &&
       cl->endian == endian)
     {
       cd = cl->cd;
       break;
     }
  }
--- 387,420 ----
  #endif
 
  #ifdef CGEN_COMPUTE_ISA
!   {
!     static CGEN_BITSET *permanent_isa;
!
!     if (!permanent_isa)
!       permanent_isa = cgen_bitset_create (MAX_ISAS);
!     isa = permanent_isa;
!     cgen_bitset_clear (isa);
!     cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
!   }
  #else
    isa = info->insn_sets;
  #endif
 
    /* If we've switched cpu's, try to find a handle we've used before */
    if (cd
!       && (cgen_bitset_compare (isa, prev_isa) != 0
   || mach != prev_mach
   || endian != prev_endian))
      {
        cd = 0;
        for (cl = cd_list; cl; cl = cl->next)
  {
!  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
       cl->mach == mach &&
       cl->endian == endian)
     {
       cd = cl->cd;
+        prev_isa = cd->isas;
       break;
     }
  }
*************** print_insn_@arch@ (bfd_vma pc, disassemb
*** 420,426 ****
  abort ();
        mach_name = arch_type->printable_name;
 
!       prev_isa = isa;
        prev_mach = mach;
        prev_endian = endian;
        cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
--- 430,436 ----
  abort ();
        mach_name = arch_type->printable_name;
 
!       prev_isa = cgen_bitset_copy (isa);
        prev_mach = mach;
        prev_endian = endian;
        cd = @arch@_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
*************** print_insn_@arch@ (bfd_vma pc, disassemb
*** 433,439 ****
        /* Save this away for future reference.  */
        cl = xmalloc (sizeof (struct cpu_desc_list));
        cl->cd = cd;
!       cl->isa = isa;
        cl->mach = mach;
        cl->endian = endian;
        cl->next = cd_list;
--- 443,449 ----
        /* Save this away for future reference.  */
        cl = xmalloc (sizeof (struct cpu_desc_list));
        cl->cd = cd;
!       cl->isa = prev_isa;
        cl->mach = mach;
        cl->endian = endian;
        cl->next = cd_list;
Index: opcodes/cgen-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/cgen-opc.c,v
retrieving revision 1.15
diff -c -p -r1.15 cgen-opc.c
*** opcodes/cgen-opc.c 1 Jul 2005 11:16:31 -0000 1.15
--- opcodes/cgen-opc.c 19 Sep 2005 19:48:54 -0000
*************** cgen_signed_overflow_ok_p (CGEN_CPU_DESC
*** 613,615 ****
--- 613,763 ----
  {
    return cd->signed_overflow_ok_p;
  }
+ /* Functions for manipulating CGEN_BITSET.  */
+
+ /* Create a bit mask.  */
+ CGEN_BITSET *
+ cgen_bitset_create (unsigned bit_count)
+ {
+   CGEN_BITSET * mask = xmalloc (sizeof (* mask));
+   cgen_bitset_init (mask, bit_count);
+   return mask;
+ }
+
+ /* Initialize an existing bit mask.  */
+
+ void
+ cgen_bitset_init (CGEN_BITSET * mask, unsigned bit_count)
+ {
+   if (! mask)
+     return;
+   mask->length = (bit_count / 8) + 1;
+   mask->bits = xmalloc (mask->length);
+   cgen_bitset_clear (mask);
+ }
+
+ /* Clear the bits of a bit mask.  */
+
+ void
+ cgen_bitset_clear (CGEN_BITSET * mask)
+ {
+   unsigned i;
+
+   if (! mask)
+     return;
+
+   for (i = 0; i < mask->length; ++i)
+     mask->bits[i] = 0;
+ }
+
+ /* Add a bit to a bit mask.  */
+
+ void
+ cgen_bitset_add (CGEN_BITSET * mask, unsigned bit_num)
+ {
+   int byte_ix, bit_ix;
+   int bit_mask;
+
+   if (! mask)
+     return;
+   byte_ix = bit_num / 8;
+   bit_ix = bit_num % 8;
+   bit_mask = 1 << (7 - bit_ix);
+   mask->bits[byte_ix] |= bit_mask;
+ }
+
+ /* Set a bit mask.  */
+
+ void
+ cgen_bitset_set (CGEN_BITSET * mask, unsigned bit_num)
+ {
+   if (! mask)
+     return;
+   cgen_bitset_clear (mask);
+   cgen_bitset_add (mask, bit_num);
+ }
+
+ /* Test for a bit in a bit mask.
+    Returns 1 if the bit is found  */
+
+ int
+ cgen_bitset_contains (CGEN_BITSET * mask, unsigned bit_num)
+ {
+   int byte_ix, bit_ix;
+   int bit_mask;
+
+   if (! mask)
+     return 1; /* No bit restrictions.  */
+
+   byte_ix = bit_num / 8;
+   bit_ix = 7 - (bit_num % 8);
+   bit_mask = 1 << bit_ix;
+   return (mask->bits[byte_ix] & bit_mask) >> bit_ix;
+ }
+
+ /* Compare two bit masks for equality.
+    Returns 0 if they are equal.  */
+
+ int
+ cgen_bitset_compare (CGEN_BITSET * mask1, CGEN_BITSET * mask2)
+ {
+   if (mask1 == mask2)
+     return 0;
+   if (! mask1 || ! mask2)
+     return 1;
+   if (mask1->length != mask2->length)
+     return 1;
+   return memcmp (mask1->bits, mask2->bits, mask1->length);
+ }
+
+ /* Test two bit masks for common bits.
+    Returns 1 if a common bit is found.  */
+
+ int
+ cgen_bitset_intersect_p (CGEN_BITSET * mask1, CGEN_BITSET * mask2)
+ {
+   unsigned i, limit;
+
+   if (mask1 == mask2)
+     return 1;
+   if (! mask1 || ! mask2)
+     return 0;
+   limit = mask1->length < mask2->length ? mask1->length : mask2->length;
+
+   for (i = 0; i < limit; ++i)
+     if ((mask1->bits[i] & mask2->bits[i]))
+       return 1;
+
+   return 0;
+ }
+
+ /* Make a copy of a bit mask.  */
+
+ CGEN_BITSET *
+ cgen_bitset_copy (CGEN_BITSET * mask)
+ {
+   CGEN_BITSET* newmask;
+
+   if (! mask)
+     return NULL;
+   newmask = cgen_bitset_create ((mask->length * 8) - 1);
+   memcpy (newmask->bits, mask->bits, mask->length);
+   return newmask;
+ }
+
+ /* Combine two bit masks.  */
+
+ void
+ cgen_bitset_union (CGEN_BITSET * mask1, CGEN_BITSET * mask2,
+   CGEN_BITSET * result)
+ {
+   unsigned i;
+
+   if (! mask1 || ! mask2 || ! result
+       || mask1->length != mask2->length
+       || mask1->length != result->length)
+     return;
+
+   for (i = 0; i < result->length; ++i)
+     result->bits[i] = mask1->bits[i] | mask2->bits[i];
+ }
Index: opcodes/disassemble.c
===================================================================
RCS file: /cvs/src/src/opcodes/disassemble.c,v
retrieving revision 1.56
diff -c -p -r1.56 disassemble.c
*** opcodes/disassemble.c 18 Aug 2005 03:49:00 -0000 1.56
--- opcodes/disassemble.c 19 Sep 2005 19:48:54 -0000
*************** disassemble_init_for_target (struct disa
*** 440,453 ****
  #ifdef ARCH_tic4x
      case bfd_arch_tic4x:
        info->skip_zeroes = 32;
  #endif
  #ifdef ARCH_m32c
      case bfd_arch_m32c:
        info->endian = BFD_ENDIAN_BIG;
!       if (info->mach == bfd_mach_m16c)
! info->insn_sets = 1 << ISA_M16C;
!       else
! info->insn_sets = 1 << ISA_M32C;
        break;
  #endif
      default:
--- 440,458 ----
  #ifdef ARCH_tic4x
      case bfd_arch_tic4x:
        info->skip_zeroes = 32;
+       break;
  #endif
  #ifdef ARCH_m32c
      case bfd_arch_m32c:
        info->endian = BFD_ENDIAN_BIG;
!       if (! info->insn_sets)
! {
!  info->insn_sets = cgen_bitset_create (ISA_MAX);
!  if (info->mach == bfd_mach_m16c)
!    cgen_bitset_set (info->insn_sets, ISA_M16C);
!  else
!    cgen_bitset_set (info->insn_sets, ISA_M32C);
! }
        break;
  #endif
      default:
Index: opcodes/frv-desc.c
===================================================================
RCS file: /cvs/src/src/opcodes/frv-desc.c,v
retrieving revision 1.21
diff -c -p -r1.21 frv-desc.c
*** opcodes/frv-desc.c 1 Jul 2005 11:16:31 -0000 1.21
--- opcodes/frv-desc.c 19 Sep 2005 19:48:55 -0000
*************** static const CGEN_MACH frv_cgen_mach_tab
*** 296,367 ****
 
  static CGEN_KEYWORD_ENTRY frv_cgen_opval_gr_names_entries[] =
  {
!   { "sp", 1, {0, {0}}, 0, 0 },
!   { "fp", 2, {0, {0}}, 0, 0 },
!   { "gr0", 0, {0, {0}}, 0, 0 },
!   { "gr1", 1, {0, {0}}, 0, 0 },
!   { "gr2", 2, {0, {0}}, 0, 0 },
!   { "gr3", 3, {0, {0}}, 0, 0 },
!   { "gr4", 4, {0, {0}}, 0, 0 },
!   { "gr5", 5, {0, {0}}, 0, 0 },
!   { "gr6", 6, {0, {0}}, 0, 0 },
!   { "gr7", 7, {0, {0}}, 0, 0 },
!   { "gr8", 8, {0, {0}}, 0, 0 },
!   { "gr9", 9, {0, {0}}, 0, 0 },
!   { "gr10", 10, {0, {0}}, 0, 0 },
!   { "gr11", 11, {0, {0}}, 0, 0 },
!   { "gr12", 12, {0, {0}}, 0, 0 },
!   { "gr13", 13, {0, {0}}, 0, 0 },
!   { "gr14", 14, {0, {0}}, 0, 0 },
!   { "gr15", 15, {0, {0}}, 0, 0 },
!   { "gr16", 16, {0, {0}}, 0, 0 },
!   { "gr17", 17, {0, {0}}, 0, 0 },
!   { "gr18", 18, {0, {0}}, 0, 0 },
!   { "gr19", 19, {0, {0}}, 0, 0 },
!   { "gr20", 20, {0, {0}}, 0, 0 },
!   { "gr21", 21, {0, {0}}, 0, 0 },
!   { "gr22", 22, {0, {0}}, 0, 0 },
!   { "gr23", 23, {0, {0}}, 0, 0 },
!   { "gr24", 24, {0, {0}}, 0, 0 },
!   { "gr25", 25, {0, {0}}, 0, 0 },
!   { "gr26", 26, {0, {0}}, 0, 0 },
!   { "gr27", 27, {0, {0}}, 0, 0 },
!   { "gr28", 28, {0, {0}}, 0, 0 },
!   { "gr29", 29, {0, {0}}, 0, 0 },
!   { "gr30", 30, {0, {0}}, 0, 0 },
!   { "gr31", 31, {0, {0}}, 0, 0 },
!   { "gr32", 32, {0, {0}}, 0, 0 },
!   { "gr33", 33, {0, {0}}, 0, 0 },
!   { "gr34", 34, {0, {0}}, 0, 0 },
!   { "gr35", 35, {0, {0}}, 0, 0 },
!   { "gr36", 36, {0, {0}}, 0, 0 },
!   { "gr37", 37, {0, {0}}, 0, 0 },
!   { "gr38", 38, {0, {0}}, 0, 0 },
!   { "gr39", 39, {0, {0}}, 0, 0 },
!   { "gr40", 40, {0, {0}}, 0, 0 },
!   { "gr41", 41, {0, {0}}, 0, 0 },
!   { "gr42", 42, {0, {0}}, 0, 0 },
!   { "gr43", 43, {0, {0}}, 0, 0 },
!   { "gr44", 44, {0, {0}}, 0, 0 },
!   { "gr45", 45, {0, {0}}, 0, 0 },
!   { "gr46", 46, {0, {0}}, 0, 0 },
!   { "gr47", 47, {0, {0}}, 0, 0 },
!   { "gr48", 48, {0, {0}}, 0, 0 },
!   { "gr49", 49, {0, {0}}, 0, 0 },
!   { "gr50", 50, {0, {0}}, 0, 0 },
!   { "gr51", 51, {0, {0}}, 0, 0 },
!   { "gr52", 52, {0, {0}}, 0, 0 },
!   { "gr53", 53, {0, {0}}, 0, 0 },
!   { "gr54", 54, {0, {0}}, 0, 0 },
!   { "gr55", 55, {0, {0}}, 0, 0 },
!   { "gr56", 56, {0, {0}}, 0, 0 },
!   { "gr57", 57, {0, {0}}, 0, 0 },
!   { "gr58", 58, {0, {0}}, 0, 0 },
!   { "gr59", 59, {0, {0}}, 0, 0 },
!   { "gr60", 60, {0, {0}}, 0, 0 },
!   { "gr61", 61, {0, {0}}, 0, 0 },
!   { "gr62", 62, {0, {0}}, 0, 0 },
!   { "gr
Reply | Threaded
Open this post in threaded view
|

Re: [patch][rfa] Representation of ISA Attribute in CGEN

Dave Brolley-2
This patch has now been committed.....

Dave Brolley wrote:

> Hi,
>
> These changes have been in our local tree for a few years now and were
> developed for an internal port which requires *much* more than 32 ISAs
> or even 64 ISAs. These changes could be of benifit to others, so I
> would like to submit them for approval.
>
> Currently, ISA is represented as an integer, like all the other
> non-boolean attributes. It is a bit mask with each bit representing
> whether a particular ISA is supported. Our port requires that there be
> no fixed limit on the number of ISAs, and so, we developed an
> open-ended representation for a bitset using a bitstring and a length.
> It is called CGEN_BITSET and is declared in
> include/opcode/cgen-bitset.h and supported by several new functions in
> opcodes/cgen-opc.c. All manipulation of these bitsets is done using
> these functions which hide the internal representation. See
> cgen-bitset.h (attached) for a description of the implementation
>
> The patch has 3 parts:
> 1) Extension of CGEN_ATTR_VALUE_TYPE to be a union allowing the use of
> CGEN_BITSET as well as its supporting macros.
>
> 2) Changes to CGEN so that it generates code to correctly access and
> initialize the new definition of CGEN_ATTR_VALUE_TYPE and to use the
> proper cover functions when manipulating ISAs.
>
> 3) Changes to hand written portions of existing opcodes, sim and sid
> ports as in 2). Fortunately, the use of existing CGEN macros made
> these changes minimal.
>
> I have also included in the patch the regenerated source for the frv
> port so that you can see the effect on the generated code. None of the
> generated code for existing sid ports is affected.
>
> One natural extension of this work would be use the same
> representation for all bitset attributes in CGEN. I believe that MACH
> is the only other one at this time.
>
> Seeking comments and approval to commit.
>
> Thanks,
> Dave
>