[patch,arm] Incorrect opcode for SEL insn

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[patch,arm] Incorrect opcode for SEL insn

Paul Brook
The attached patch corrects the encoding of the Arm SEL instruction.

Tested with cross to arm-none-eabi.
Ok?

Paul

2005-10-26  Paul Brook  <[hidden email]>

gas/
        * config/tc-arm.c (insns): Correct "sel" entry.
gas/testsuite/
        * gas/arm/archv6.d: Adjust expected output.
opcodes/
        * arm-dis.c (arm_opcodes): Correct "sel" entry.

Index: gas/config/tc-arm.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/config/tc-arm.c,v
retrieving revision 1.230
diff -u -p -r1.230 tc-arm.c
--- gas/config/tc-arm.c 8 Oct 2005 17:07:15 -0000 1.230
+++ gas/config/tc-arm.c 26 Oct 2005 12:40:50 -0000
@@ -8928,7 +8928,7 @@ static const struct asm_opcode insns[] =
  TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
  TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
  TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR),   sxth,  t_sxth),
- TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc),   rd_rn_rm, t_simd),
+ TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc),   rd_rn_rm, t_simd),
  TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
  TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
  TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
Index: gas/testsuite/gas/arm/archv6.d
===================================================================
RCS file: /var/cvsroot/src-cvs/src/gas/testsuite/gas/arm/archv6.d,v
retrieving revision 1.2
diff -u -p -r1.2 archv6.d
--- gas/testsuite/gas/arm/archv6.d 22 Dec 2003 08:43:41 -0000 1.2
+++ gas/testsuite/gas/arm/archv6.d 26 Oct 2005 13:19:12 -0000
@@ -64,8 +64,8 @@ Disassembly of section .text:
 0+0e0 <[^>]*> 16a42475 ? sxtabne r2, r4, r5, ROR #8
 0+0e4 <[^>]*> e6142f37 ? saddaddx r2, r4, r7
 0+0e8 <[^>]*> 16142f37 ? saddaddxne r2, r4, r7
-0+0ec <[^>]*> e68210b3 ? sel r1, r2, r3
-0+0f0 <[^>]*> 168210b3 ? selne r1, r2, r3
+0+0ec <[^>]*> e6821fb3 ? sel r1, r2, r3
+0+0f0 <[^>]*> 16821fb3 ? selne r1, r2, r3
 0+0f4 <[^>]*> f1010200 ? setend be
 0+0f8 <[^>]*> f1010000 ? setend le
 0+0fc <[^>]*> e6342f17 ? shadd16 r2, r4, r7
Index: opcodes/arm-dis.c
===================================================================
RCS file: /var/cvsroot/src-cvs/src/opcodes/arm-dis.c,v
retrieving revision 1.57
diff -u -p -r1.57 arm-dis.c
--- opcodes/arm-dis.c 8 Oct 2005 14:52:07 -0000 1.57
+++ opcodes/arm-dis.c 26 Oct 2005 12:31:28 -0000
@@ -557,7 +557,7 @@ static const struct opcode32 arm_opcodes
   {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
   {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
   {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
-  {ARM_EXT_V6, 0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
+  {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
   {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
   {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
   {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
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Re: [patch,arm] Incorrect opcode for SEL insn

Richard Earnshaw-2
On Wed, 2005-10-26 at 14:27, Paul Brook wrote:

> The attached patch corrects the encoding of the Arm SEL instruction.
>
> Tested with cross to arm-none-eabi.
> Ok?
>
> Paul
>
> 2005-10-26  Paul Brook  <[hidden email]>
>
> gas/
> * config/tc-arm.c (insns): Correct "sel" entry.
> gas/testsuite/
> * gas/arm/archv6.d: Adjust expected output.
> opcodes/
> * arm-dis.c (arm_opcodes): Correct "sel" entry.

OK.

R.