[mep] configuration regen

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[mep] configuration regen

DJ Delorie-2

Toshiba has requested a new default configuration.  This is a regen of
affected files.  Ok to apply?

Index: sid/component/cgen-cpu/ChangeLog
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/ChangeLog,v
retrieving revision 1.81
diff -p -U3 -r1.81  sid/component/cgen-cpu/ChangeLog
--- sid/component/cgen-cpu/ChangeLog 5 Feb 2007 20:28:39 -0000 1.81
+++ sid/component/cgen-cpu/ChangeLog 3 Feb 2009 01:53:50 -0000
@@ -1,3 +1,7 @@
+2009-02-02  DJ Delorie  <[hidden email]>
+
+ * compCGEN.cxx: Update to new MeP configuration.
+
 2007-02-05  Dave Brolley  <[hidden email]>
 
  * Contribute the following changes:
Index: sid/component/cgen-cpu/compCGEN.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/compCGEN.cxx,v
retrieving revision 1.22
diff -p -U3 -r1.22  sid/component/cgen-cpu/compCGEN.cxx
--- sid/component/cgen-cpu/compCGEN.cxx 5 Feb 2007 20:28:39 -0000 1.22
+++ sid/component/cgen-cpu/compCGEN.cxx 3 Feb 2009 01:53:50 -0000
@@ -30,7 +30,6 @@ extern "C" {
 #include "mep_basic.h"
 // begin-mep-includes
 #include "mep_ext1.h"
-#include "mep_ext2.h"
 // end-mep-includes
 #endif
 #if SIDTARGET_MT
@@ -331,7 +330,6 @@ compCGENListTypes ()
   types.push_back ("hw-cpu-mep");
   // begin-mep-types
   types.push_back ("hw-cpu-mep-ext1");
-  types.push_back ("hw-cpu-mep-ext2");
   // end-mep-types
 #endif
 #if SIDTARGET_MT
@@ -383,8 +381,6 @@ compCGENCreate (const string& typeName)
   // begin-mep-constructors
   if (typeName == "hw-cpu-mep-ext1")
     return new mep_ext1::mep_ext1_cpu ();
-  if (typeName == "hw-cpu-mep-ext2")
-    return new mep_ext2::mep_ext2_cpu ();
   // end-mep-constructors
 #endif
 #if SIDTARGET_MT
Index: sid/component/cgen-cpu/mep/ChangeLog
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/ChangeLog,v
retrieving revision 1.2
diff -p -U3 -r1.2  sid/component/cgen-cpu/mep/ChangeLog
--- sid/component/cgen-cpu/mep/ChangeLog 13 Aug 2007 14:47:43 -0000 1.2
+++ sid/component/cgen-cpu/mep/ChangeLog 3 Feb 2009 01:53:51 -0000
@@ -1,3 +1,14 @@
+2009-02-02  DJ Delorie  <[hidden email]>
+
+ * Makefile.am: Update to new MeP configuration.
+ * Makefile.in: Likewise.
+ * common_model.cxx: Likewise.
+ * mep-core1-decode.cxx: Likewise.
+ * mep-cpu.h: Likewise.
+ * mep-decode.cxx: Likewise.
+ * mep-desc.h: Likewise.
+ * mep.h: Likewise.
+
 2007-08-13  Frank Ch. Eigler  <[hidden email]>
 
  * common_model.h: Change #include guard name.
Index: sid/component/cgen-cpu/mep/Makefile.am
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/Makefile.am,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/Makefile.am
--- sid/component/cgen-cpu/mep/Makefile.am 5 Feb 2007 20:28:39 -0000 1.1
+++ sid/component/cgen-cpu/mep/Makefile.am 3 Feb 2009 01:53:51 -0000
@@ -11,7 +11,7 @@ CXXFLAGS = $(TOP_CXXFLAGS) -DHAVE_CONFIG
 
 pkgdata_DATA = hw-cpu-mep.txt
 
-CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx mep-core2-decode.cxx mep-core2-sem.cxx mep-core2-model.cxx mep-cop2-16-decode.cxx mep-cop2-16-sem.cxx mep-cop2-16-model.cxx mep-cop2-32-decode.cxx mep-cop2-32-sem.cxx mep-cop2-32-model.cxx mep-cop2-48-decode.cxx mep-cop2-48-sem.cxx mep-cop2-48-model.cxx mep-cop2-64-decode.cxx mep-cop2-64-sem.cxx mep-cop2-64-model.cxx fmax-fp.cxx fmax-fpu.cxx
+CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx
 
 libmep_la_SOURCES = mep.cxx common_model.cxx mep-decode.cxx mep-sem.cxx mep-model.cxx $(CPU_SOURCES)
 libmep_la_LDFLAGS =
@@ -57,9 +57,9 @@ CGENDEPS = ../../../../cgen/stamp-cgen \
         $(cgendir)/sim-test.scm  $(cgendir)/sim-cpu.scm \
         $(cgendir)/sim-model.scm $(cgendir)/sim.scm
 
-CPU_TARGETS = mep-core1 mep-core2 mep-cop2-16 mep-cop2-32 mep-cop2-48 mep-cop2-64
+CPU_TARGETS = mep-core1
 
-CPU_LIST = mep,ext_core1,ext_core2,ext_cop2_16,ext_cop2_32,ext_cop2_48,ext_cop2_64
+CPU_LIST = mep,ext_core1
 
 CGEN_TARGETS = mep-cpudesc mep-decsemdefs $(CPU_TARGETS)
 .PHONY: $(CGEN_TARGETS)
@@ -73,31 +73,6 @@ mep-core1:
  mep "with-multiple-isa with-scache with-profile=fn" mep_ext1 ext_core1 $(CGEN_MACH) mepcore1 "mep-core1-" \
  $(cgendir)/cpu/mep.cpu \
  "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-core2:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_core2 $(CGEN_MACH) mepcore2 "mep-core2-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-16:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_16 $(CGEN_MACH) mepcop2_16 "mep-cop2-16-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-32:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_32 $(CGEN_MACH) mepcop2_32 "mep-cop2-32-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-48:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_48 $(CGEN_MACH) mepcop2_48 "mep-cop2-48-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-64:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_64 $(CGEN_MACH) mepcop2_64 "mep-cop2-64-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
 # end-cpus
 mep-cpudesc:
  $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
Index: sid/component/cgen-cpu/mep/Makefile.in
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/Makefile.in,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/Makefile.in
--- sid/component/cgen-cpu/mep/Makefile.in 5 Feb 2007 20:28:39 -0000 1.1
+++ sid/component/cgen-cpu/mep/Makefile.in 3 Feb 2009 01:53:51 -0000
@@ -74,13 +74,8 @@ CONFIG_CLEAN_FILES =
 LTLIBRARIES = $(noinst_LTLIBRARIES)
 libmep_la_DEPENDENCIES = mep-asm.lo mep-dis.lo mep-opc.lo mep-ibld.lo \
  mep-desc.lo
-am__objects_1 = mep-core1-decode.lo mep-core1-sem.lo \
- mep-core1-model.lo mep-core2-decode.lo mep-core2-sem.lo \
- mep-core2-model.lo mep-cop2-16-decode.lo mep-cop2-16-sem.lo \
- mep-cop2-16-model.lo mep-cop2-32-decode.lo mep-cop2-32-sem.lo \
- mep-cop2-32-model.lo mep-cop2-48-decode.lo mep-cop2-48-sem.lo \
- mep-cop2-48-model.lo mep-cop2-64-decode.lo mep-cop2-64-sem.lo \
- mep-cop2-64-model.lo fmax-fp.lo fmax-fpu.lo
+am__objects_1 = \
+mep-core1-decode.lo mep-core1-sem.lo mep-core1-model.lo
 am_libmep_la_OBJECTS = mep.lo common_model.lo mep-decode.lo mep-sem.lo \
  mep-model.lo $(am__objects_1)
 libmep_la_OBJECTS = $(am_libmep_la_OBJECTS)
@@ -241,7 +236,7 @@ noinst_LTLIBRARIES = libmep.la
 BFDINCLUDES = -I../../../../bfd -I$(srcdir)/../../../../include
 INCLUDES = -I$(srcdir) -I$(srcdir)/.. -I.. -I../../../include -I$(srcdir)/../../../include $(BFDINCLUDES)
 pkgdata_DATA = hw-cpu-mep.txt
-CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx mep-core2-decode.cxx mep-core2-sem.cxx mep-core2-model.cxx mep-cop2-16-decode.cxx mep-cop2-16-sem.cxx mep-cop2-16-model.cxx mep-cop2-32-decode.cxx mep-cop2-32-sem.cxx mep-cop2-32-model.cxx mep-cop2-48-decode.cxx mep-cop2-48-sem.cxx mep-cop2-48-model.cxx mep-cop2-64-decode.cxx mep-cop2-64-sem.cxx mep-cop2-64-model.cxx fmax-fp.cxx fmax-fpu.cxx
+CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx
 libmep_la_SOURCES = mep.cxx common_model.cxx mep-decode.cxx mep-sem.cxx mep-model.cxx $(CPU_SOURCES)
 libmep_la_LDFLAGS =
 libmep_la_LIBADD = mep-asm.lo mep-dis.lo mep-opc.lo mep-ibld.lo mep-desc.lo
@@ -264,8 +259,8 @@ CGENDEPS = ../../../../cgen/stamp-cgen \
         $(cgendir)/sim-test.scm  $(cgendir)/sim-cpu.scm \
         $(cgendir)/sim-model.scm $(cgendir)/sim.scm
 
-CPU_TARGETS = mep-core1 mep-core2 mep-cop2-16 mep-cop2-32 mep-cop2-48 mep-cop2-64
-CPU_LIST = mep,ext_core1,ext_core2,ext_cop2_16,ext_cop2_32,ext_cop2_48,ext_cop2_64
+CPU_TARGETS = mep-core1
+CPU_LIST = mep,ext_core1
 CGEN_TARGETS = mep-cpudesc mep-decsemdefs $(CPU_TARGETS)
 html_stylesheet = $(srcdir)/../../component_html.xsl
 SUFFIXES = .xml .txt .html
@@ -325,26 +320,9 @@ distclean-compile:
  -rm -f *.tab.c
 
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/common_model.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fmax-fp.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fmax-fpu.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-16-decode.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-16-model.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-16-sem.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-32-decode.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-32-model.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-32-sem.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-48-decode.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-48-model.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-48-sem.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-64-decode.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-64-model.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-64-sem.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core1-decode.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core1-model.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core1-sem.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core2-decode.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core2-model.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core2-sem.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-decode.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-model.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-sem.Plo@am__quote@
@@ -703,31 +681,6 @@ mep-core1:
  mep "with-multiple-isa with-scache with-profile=fn" mep_ext1 ext_core1 $(CGEN_MACH) mepcore1 "mep-core1-" \
  $(cgendir)/cpu/mep.cpu \
  "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-core2:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_core2 $(CGEN_MACH) mepcore2 "mep-core2-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-16:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_16 $(CGEN_MACH) mepcop2_16 "mep-cop2-16-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-32:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_32 $(CGEN_MACH) mepcop2_32 "mep-cop2-32-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-48:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_48 $(CGEN_MACH) mepcop2_48 "mep-cop2-48-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
-mep-cop2-64:
- $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
- mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_64 $(CGEN_MACH) mepcop2_64 "mep-cop2-64-" \
- $(cgendir)/cpu/mep.cpu \
- "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
 # end-cpus
 mep-cpudesc:
  $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
Index: sid/component/cgen-cpu/mep/common_model.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/common_model.cxx,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/common_model.cxx
--- sid/component/cgen-cpu/mep/common_model.cxx 5 Feb 2007 20:28:40 -0000 1.1
+++ sid/component/cgen-cpu/mep/common_model.cxx 3 Feb 2009 01:53:51 -0000
@@ -10,14 +10,12 @@
 #include "mep_basic.h"
 // begin-includes
 #include "mep_ext1.h"
-#include "mep_ext2.h"
 // end-includes
 
 using namespace cgen;
 using namespace mep_basic;
 // begin-namespaces
 using namespace mep_ext1;
-using namespace mep_ext2;
 // end-namespaces
 
 // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
@@ -40,11 +38,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_ldcb_before (mep_basic_cpu *, const mep_idesc *, int unit_num);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_ldcb_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -59,11 +52,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_divide_before (mep_basic_cpu *, const mep_idesc *, int unit_num);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_divide_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -78,11 +66,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_multiply_before (mep_basic_cpu *, const mep_idesc *, int unit_num);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_multiply_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -97,11 +80,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_use_ctrl_reg_before (mep_basic_cpu *, const mep_idesc *, int unit_num, INT usereg);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_use_ctrl_reg_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, INT usereg);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -117,11 +95,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_use_gpr_before (mep_basic_cpu *, const mep_idesc *, int unit_num, INT usereg);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_use_gpr_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, INT usereg);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, INT usereg);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -144,11 +117,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_branch_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_branch_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -166,11 +134,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_multiply_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_multiply_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -188,11 +151,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_stcb_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_stcb_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -217,11 +175,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_divide_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_divide_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -241,11 +194,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_load_gpr_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_load_gpr_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -265,11 +213,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_ldcb_gpr_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_ldcb_gpr_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -289,11 +232,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_mul_gpr_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
 template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_mul_gpr_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
-template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
-template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
-template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
-template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
-template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
 // end-generated-instantiations
 
 template <class BASE, class CPU, class IDESC, class SCACHE>
@@ -330,9 +268,4 @@ mep_common_model<BASE, CPU, IDESC, SCACH
 // begin-generated-instantiations
 template void mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::step_latency (sid::host_int_4 cycles);
 template void mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::step_latency (sid::host_int_4 cycles);
-template void mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::step_latency (sid::host_int_4 cycles);
-template void mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::step_latency (sid::host_int_4 cycles);
-template void mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::step_latency (sid::host_int_4 cycles);
-template void mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::step_latency (sid::host_int_4 cycles);
-template void mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::step_latency (sid::host_int_4 cycles);
 // end-generated-instantiations
Index: sid/component/cgen-cpu/mep/mep-core1-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-core1-decode.cxx,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-core1-decode.cxx
--- sid/component/cgen-cpu/mep/mep-core1-decode.cxx 5 Feb 2007 20:28:40 -0000 1.1
+++ sid/component/cgen-cpu/mep/mep-core1-decode.cxx 3 Feb 2009 01:53:51 -0000
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
 
 This file is part of the Red Hat simulators.
 
@@ -23,213 +23,213 @@ using namespace mep_ext1; // FIXME: name
 mepcore1_idesc mepcore1_idesc::idesc_table[MEPCORE1_INSN_RI_19 + 1] =
 {
   { mepcore1_sem_x_invalid, "X_INVALID", MEPCORE1_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x40" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sb, "SB", MEPCORE1_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sh, "SH", MEPCORE1_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sw, "SW", MEPCORE1_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lb, "LB", MEPCORE1_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lh, "LH", MEPCORE1_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lw, "LW", MEPCORE1_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lbu, "LBU", MEPCORE1_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lhu, "LHU", MEPCORE1_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_sw_sp, "SW_SP", MEPCORE1_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lw_sp, "LW_SP", MEPCORE1_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_sb_tp, "SB_TP", MEPCORE1_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sh_tp, "SH_TP", MEPCORE1_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sw_tp, "SW_TP", MEPCORE1_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lb_tp, "LB_TP", MEPCORE1_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lh_tp, "LH_TP", MEPCORE1_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lw_tp, "LW_TP", MEPCORE1_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lbu_tp, "LBU_TP", MEPCORE1_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lhu_tp, "LHU_TP", MEPCORE1_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_sb16, "SB16", MEPCORE1_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sh16, "SH16", MEPCORE1_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sw16, "SW16", MEPCORE1_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lb16, "LB16", MEPCORE1_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lh16, "LH16", MEPCORE1_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lw16, "LW16", MEPCORE1_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lbu16, "LBU16", MEPCORE1_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_lhu16, "LHU16", MEPCORE1_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_sw24, "SW24", MEPCORE1_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lw24, "LW24", MEPCORE1_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_extb, "EXTB", MEPCORE1_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_exth, "EXTH", MEPCORE1_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_extub, "EXTUB", MEPCORE1_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_extuh, "EXTUH", MEPCORE1_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ssarb, "SSARB", MEPCORE1_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_mov, "MOV", MEPCORE1_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_movi8, "MOVI8", MEPCORE1_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_movi16, "MOVI16", MEPCORE1_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_movu24, "MOVU24", MEPCORE1_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_movu16, "MOVU16", MEPCORE1_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_movh, "MOVH", MEPCORE1_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_add3, "ADD3", MEPCORE1_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_add, "ADD", MEPCORE1_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_add3i, "ADD3I", MEPCORE1_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_advck3, "ADVCK3", MEPCORE1_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sub, "SUB", MEPCORE1_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sbvck3, "SBVCK3", MEPCORE1_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_neg, "NEG", MEPCORE1_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_slt3, "SLT3", MEPCORE1_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sltu3, "SLTU3", MEPCORE1_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_slt3i, "SLT3I", MEPCORE1_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sltu3i, "SLTU3I", MEPCORE1_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sl1ad3, "SL1AD3", MEPCORE1_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sl2ad3, "SL2AD3", MEPCORE1_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_add3x, "ADD3X", MEPCORE1_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_slt3x, "SLT3X", MEPCORE1_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sltu3x, "SLTU3X", MEPCORE1_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_or, "OR", MEPCORE1_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_and, "AND", MEPCORE1_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_xor, "XOR", MEPCORE1_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_nor, "NOR", MEPCORE1_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_or3, "OR3", MEPCORE1_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_and3, "AND3", MEPCORE1_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_xor3, "XOR3", MEPCORE1_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sra, "SRA", MEPCORE1_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_srl, "SRL", MEPCORE1_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sll, "SLL", MEPCORE1_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_srai, "SRAI", MEPCORE1_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_srli, "SRLI", MEPCORE1_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_slli, "SLLI", MEPCORE1_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sll3, "SLL3", MEPCORE1_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_fsft, "FSFT", MEPCORE1_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bra, "BRA", MEPCORE1_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_beqz, "BEQZ", MEPCORE1_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bnez, "BNEZ", MEPCORE1_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_beqi, "BEQI", MEPCORE1_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bnei, "BNEI", MEPCORE1_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_blti, "BLTI", MEPCORE1_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bgei, "BGEI", MEPCORE1_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_beq, "BEQ", MEPCORE1_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bne, "BNE", MEPCORE1_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bsr12, "BSR12", MEPCORE1_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bsr24, "BSR24", MEPCORE1_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_jmp, "JMP", MEPCORE1_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_jmp24, "JMP24", MEPCORE1_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_jsr, "JSR", MEPCORE1_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ret, "RET", MEPCORE1_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_repeat, "REPEAT", MEPCORE1_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_erepeat, "EREPEAT", MEPCORE1_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_stc_lp, "STC_LP", MEPCORE1_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_stc_hi, "STC_HI", MEPCORE1_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_stc_lo, "STC_LO", MEPCORE1_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_stc, "STC", MEPCORE1_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ldc_lp, "LDC_LP", MEPCORE1_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ldc_hi, "LDC_HI", MEPCORE1_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ldc_lo, "LDC_LO", MEPCORE1_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ldc, "LDC", MEPCORE1_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mepcore1_sem_di, "DI", MEPCORE1_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ei, "EI", MEPCORE1_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_reti, "RETI", MEPCORE1_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_halt, "HALT", MEPCORE1_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sleep, "SLEEP", MEPCORE1_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_swi, "SWI", MEPCORE1_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_break, "BREAK", MEPCORE1_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_syncm, "SYNCM", MEPCORE1_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_stcb, "STCB", MEPCORE1_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ldcb, "LDCB", MEPCORE1_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mepcore1_sem_bsetm, "BSETM", MEPCORE1_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bclrm, "BCLRM", MEPCORE1_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bnotm, "BNOTM", MEPCORE1_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_btstm, "BTSTM", MEPCORE1_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_tas, "TAS", MEPCORE1_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_cache, "CACHE", MEPCORE1_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_mul, "MUL", MEPCORE1_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_mulu, "MULU", MEPCORE1_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_mulr, "MULR", MEPCORE1_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mepcore1_sem_mulru, "MULRU", MEPCORE1_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mepcore1_sem_madd, "MADD", MEPCORE1_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_maddu, "MADDU", MEPCORE1_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_maddr, "MADDR", MEPCORE1_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mepcore1_sem_maddru, "MADDRU", MEPCORE1_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mepcore1_sem_div, "DIV", MEPCORE1_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
-  { mepcore1_sem_divu, "DIVU", MEPCORE1_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
-  { mepcore1_sem_dret, "DRET", MEPCORE1_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_dbreak, "DBREAK", MEPCORE1_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ldz, "LDZ", MEPCORE1_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_abs, "ABS", MEPCORE1_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ave, "AVE", MEPCORE1_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_min, "MIN", MEPCORE1_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_max, "MAX", MEPCORE1_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_minu, "MINU", MEPCORE1_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_maxu, "MAXU", MEPCORE1_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_clip, "CLIP", MEPCORE1_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_clipu, "CLIPU", MEPCORE1_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sadd, "SADD", MEPCORE1_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ssub, "SSUB", MEPCORE1_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_saddu, "SADDU", MEPCORE1_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ssubu, "SSUBU", MEPCORE1_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_swcp, "SWCP", MEPCORE1_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lwcp, "LWCP", MEPCORE1_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_smcp, "SMCP", MEPCORE1_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lmcp, "LMCP", MEPCORE1_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_swcpi, "SWCPI", MEPCORE1_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lwcpi, "LWCPI", MEPCORE1_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_smcpi, "SMCPI", MEPCORE1_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lmcpi, "LMCPI", MEPCORE1_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_swcp16, "SWCP16", MEPCORE1_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lwcp16, "LWCP16", MEPCORE1_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_smcp16, "SMCP16", MEPCORE1_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lmcp16, "LMCP16", MEPCORE1_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sbcpa, "SBCPA", MEPCORE1_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lbcpa, "LBCPA", MEPCORE1_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_shcpa, "SHCPA", MEPCORE1_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lhcpa, "LHCPA", MEPCORE1_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_swcpa, "SWCPA", MEPCORE1_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lwcpa, "LWCPA", MEPCORE1_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_smcpa, "SMCPA", MEPCORE1_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lmcpa, "LMCPA", MEPCORE1_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sbcpm0, "SBCPM0", MEPCORE1_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lbcpm0, "LBCPM0", MEPCORE1_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_shcpm0, "SHCPM0", MEPCORE1_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lhcpm0, "LHCPM0", MEPCORE1_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_swcpm0, "SWCPM0", MEPCORE1_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lwcpm0, "LWCPM0", MEPCORE1_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_smcpm0, "SMCPM0", MEPCORE1_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lmcpm0, "LMCPM0", MEPCORE1_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sbcpm1, "SBCPM1", MEPCORE1_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lbcpm1, "LBCPM1", MEPCORE1_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_shcpm1, "SHCPM1", MEPCORE1_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lhcpm1, "LHCPM1", MEPCORE1_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_swcpm1, "SWCPM1", MEPCORE1_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lwcpm1, "LWCPM1", MEPCORE1_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_smcpm1, "SMCPM1", MEPCORE1_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_lmcpm1, "LMCPM1", MEPCORE1_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bcpeq, "BCPEQ", MEPCORE1_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bcpne, "BCPNE", MEPCORE1_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bcpat, "BCPAT", MEPCORE1_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bcpaf, "BCPAF", MEPCORE1_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_synccp, "SYNCCP", MEPCORE1_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_jsrv, "JSRV", MEPCORE1_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_bsrv, "BSRV", MEPCORE1_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_sim_syscall, "SIM_SYSCALL", MEPCORE1_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_0, "RI_0", MEPCORE1_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_1, "RI_1", MEPCORE1_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_2, "RI_2", MEPCORE1_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_3, "RI_3", MEPCORE1_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_4, "RI_4", MEPCORE1_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_5, "RI_5", MEPCORE1_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_6, "RI_6", MEPCORE1_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_7, "RI_7", MEPCORE1_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_8, "RI_8", MEPCORE1_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_9, "RI_9", MEPCORE1_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_10, "RI_10", MEPCORE1_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_11, "RI_11", MEPCORE1_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_12, "RI_12", MEPCORE1_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_13, "RI_13", MEPCORE1_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_14, "RI_14", MEPCORE1_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_15, "RI_15", MEPCORE1_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_17, "RI_17", MEPCORE1_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_20, "RI_20", MEPCORE1_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_21, "RI_21", MEPCORE1_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_22, "RI_22", MEPCORE1_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_23, "RI_23", MEPCORE1_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_24, "RI_24", MEPCORE1_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_25, "RI_25", MEPCORE1_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_26, "RI_26", MEPCORE1_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_16, "RI_16", MEPCORE1_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_18, "RI_18", MEPCORE1_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mepcore1_sem_ri_19, "RI_19", MEPCORE1_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sb, "SB", MEPCORE1_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sh, "SH", MEPCORE1_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sw, "SW", MEPCORE1_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lb, "LB", MEPCORE1_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lh, "LH", MEPCORE1_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lw, "LW", MEPCORE1_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lbu, "LBU", MEPCORE1_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lhu, "LHU", MEPCORE1_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_sw_sp, "SW_SP", MEPCORE1_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lw_sp, "LW_SP", MEPCORE1_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_sb_tp, "SB_TP", MEPCORE1_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sh_tp, "SH_TP", MEPCORE1_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sw_tp, "SW_TP", MEPCORE1_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lb_tp, "LB_TP", MEPCORE1_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lh_tp, "LH_TP", MEPCORE1_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lw_tp, "LW_TP", MEPCORE1_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lbu_tp, "LBU_TP", MEPCORE1_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lhu_tp, "LHU_TP", MEPCORE1_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_sb16, "SB16", MEPCORE1_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sh16, "SH16", MEPCORE1_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sw16, "SW16", MEPCORE1_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lb16, "LB16", MEPCORE1_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lh16, "LH16", MEPCORE1_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lw16, "LW16", MEPCORE1_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lbu16, "LBU16", MEPCORE1_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_lhu16, "LHU16", MEPCORE1_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_sw24, "SW24", MEPCORE1_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lw24, "LW24", MEPCORE1_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_extb, "EXTB", MEPCORE1_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_exth, "EXTH", MEPCORE1_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_extub, "EXTUB", MEPCORE1_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_extuh, "EXTUH", MEPCORE1_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ssarb, "SSARB", MEPCORE1_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_mov, "MOV", MEPCORE1_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_movi8, "MOVI8", MEPCORE1_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_movi16, "MOVI16", MEPCORE1_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_movu24, "MOVU24", MEPCORE1_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_movu16, "MOVU16", MEPCORE1_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_movh, "MOVH", MEPCORE1_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_add3, "ADD3", MEPCORE1_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_add, "ADD", MEPCORE1_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_add3i, "ADD3I", MEPCORE1_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_advck3, "ADVCK3", MEPCORE1_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sub, "SUB", MEPCORE1_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sbvck3, "SBVCK3", MEPCORE1_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_neg, "NEG", MEPCORE1_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_slt3, "SLT3", MEPCORE1_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sltu3, "SLTU3", MEPCORE1_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_slt3i, "SLT3I", MEPCORE1_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sltu3i, "SLTU3I", MEPCORE1_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sl1ad3, "SL1AD3", MEPCORE1_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sl2ad3, "SL2AD3", MEPCORE1_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_add3x, "ADD3X", MEPCORE1_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_slt3x, "SLT3X", MEPCORE1_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sltu3x, "SLTU3X", MEPCORE1_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_or, "OR", MEPCORE1_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_and, "AND", MEPCORE1_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_xor, "XOR", MEPCORE1_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_nor, "NOR", MEPCORE1_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_or3, "OR3", MEPCORE1_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_and3, "AND3", MEPCORE1_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_xor3, "XOR3", MEPCORE1_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sra, "SRA", MEPCORE1_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_srl, "SRL", MEPCORE1_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sll, "SLL", MEPCORE1_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_srai, "SRAI", MEPCORE1_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_srli, "SRLI", MEPCORE1_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_slli, "SLLI", MEPCORE1_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sll3, "SLL3", MEPCORE1_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_fsft, "FSFT", MEPCORE1_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bra, "BRA", MEPCORE1_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_beqz, "BEQZ", MEPCORE1_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bnez, "BNEZ", MEPCORE1_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_beqi, "BEQI", MEPCORE1_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bnei, "BNEI", MEPCORE1_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_blti, "BLTI", MEPCORE1_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bgei, "BGEI", MEPCORE1_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_beq, "BEQ", MEPCORE1_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bne, "BNE", MEPCORE1_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bsr12, "BSR12", MEPCORE1_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bsr24, "BSR24", MEPCORE1_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_jmp, "JMP", MEPCORE1_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_jmp24, "JMP24", MEPCORE1_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_jsr, "JSR", MEPCORE1_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ret, "RET", MEPCORE1_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_repeat, "REPEAT", MEPCORE1_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_erepeat, "EREPEAT", MEPCORE1_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_stc_lp, "STC_LP", MEPCORE1_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_stc_hi, "STC_HI", MEPCORE1_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_stc_lo, "STC_LO", MEPCORE1_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_stc, "STC", MEPCORE1_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ldc_lp, "LDC_LP", MEPCORE1_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ldc_hi, "LDC_HI", MEPCORE1_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ldc_lo, "LDC_LO", MEPCORE1_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ldc, "LDC", MEPCORE1_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mepcore1_sem_di, "DI", MEPCORE1_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ei, "EI", MEPCORE1_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_reti, "RETI", MEPCORE1_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_halt, "HALT", MEPCORE1_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sleep, "SLEEP", MEPCORE1_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_swi, "SWI", MEPCORE1_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_break, "BREAK", MEPCORE1_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_syncm, "SYNCM", MEPCORE1_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_stcb, "STCB", MEPCORE1_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ldcb, "LDCB", MEPCORE1_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mepcore1_sem_bsetm, "BSETM", MEPCORE1_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bclrm, "BCLRM", MEPCORE1_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bnotm, "BNOTM", MEPCORE1_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_btstm, "BTSTM", MEPCORE1_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_tas, "TAS", MEPCORE1_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_cache, "CACHE", MEPCORE1_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_mul, "MUL", MEPCORE1_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_mulu, "MULU", MEPCORE1_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_mulr, "MULR", MEPCORE1_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mepcore1_sem_mulru, "MULRU", MEPCORE1_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mepcore1_sem_madd, "MADD", MEPCORE1_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_maddu, "MADDU", MEPCORE1_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_maddr, "MADDR", MEPCORE1_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mepcore1_sem_maddru, "MADDRU", MEPCORE1_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mepcore1_sem_div, "DIV", MEPCORE1_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
+  { mepcore1_sem_divu, "DIVU", MEPCORE1_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
+  { mepcore1_sem_dret, "DRET", MEPCORE1_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_dbreak, "DBREAK", MEPCORE1_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ldz, "LDZ", MEPCORE1_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_abs, "ABS", MEPCORE1_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ave, "AVE", MEPCORE1_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_min, "MIN", MEPCORE1_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_max, "MAX", MEPCORE1_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_minu, "MINU", MEPCORE1_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_maxu, "MAXU", MEPCORE1_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_clip, "CLIP", MEPCORE1_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_clipu, "CLIPU", MEPCORE1_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sadd, "SADD", MEPCORE1_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ssub, "SSUB", MEPCORE1_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_saddu, "SADDU", MEPCORE1_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ssubu, "SSUBU", MEPCORE1_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_swcp, "SWCP", MEPCORE1_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lwcp, "LWCP", MEPCORE1_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_smcp, "SMCP", MEPCORE1_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lmcp, "LMCP", MEPCORE1_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_swcpi, "SWCPI", MEPCORE1_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lwcpi, "LWCPI", MEPCORE1_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_smcpi, "SMCPI", MEPCORE1_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lmcpi, "LMCPI", MEPCORE1_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_swcp16, "SWCP16", MEPCORE1_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lwcp16, "LWCP16", MEPCORE1_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_smcp16, "SMCP16", MEPCORE1_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lmcp16, "LMCP16", MEPCORE1_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sbcpa, "SBCPA", MEPCORE1_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lbcpa, "LBCPA", MEPCORE1_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_shcpa, "SHCPA", MEPCORE1_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lhcpa, "LHCPA", MEPCORE1_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_swcpa, "SWCPA", MEPCORE1_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lwcpa, "LWCPA", MEPCORE1_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_smcpa, "SMCPA", MEPCORE1_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lmcpa, "LMCPA", MEPCORE1_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sbcpm0, "SBCPM0", MEPCORE1_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lbcpm0, "LBCPM0", MEPCORE1_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_shcpm0, "SHCPM0", MEPCORE1_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lhcpm0, "LHCPM0", MEPCORE1_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_swcpm0, "SWCPM0", MEPCORE1_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lwcpm0, "LWCPM0", MEPCORE1_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_smcpm0, "SMCPM0", MEPCORE1_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lmcpm0, "LMCPM0", MEPCORE1_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sbcpm1, "SBCPM1", MEPCORE1_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lbcpm1, "LBCPM1", MEPCORE1_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_shcpm1, "SHCPM1", MEPCORE1_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lhcpm1, "LHCPM1", MEPCORE1_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_swcpm1, "SWCPM1", MEPCORE1_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lwcpm1, "LWCPM1", MEPCORE1_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_smcpm1, "SMCPM1", MEPCORE1_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_lmcpm1, "LMCPM1", MEPCORE1_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bcpeq, "BCPEQ", MEPCORE1_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bcpne, "BCPNE", MEPCORE1_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bcpat, "BCPAT", MEPCORE1_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bcpaf, "BCPAF", MEPCORE1_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_synccp, "SYNCCP", MEPCORE1_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_jsrv, "JSRV", MEPCORE1_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_bsrv, "BSRV", MEPCORE1_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_sim_syscall, "SIM_SYSCALL", MEPCORE1_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_0, "RI_0", MEPCORE1_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_1, "RI_1", MEPCORE1_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_2, "RI_2", MEPCORE1_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_3, "RI_3", MEPCORE1_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_4, "RI_4", MEPCORE1_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_5, "RI_5", MEPCORE1_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_6, "RI_6", MEPCORE1_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_7, "RI_7", MEPCORE1_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_8, "RI_8", MEPCORE1_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_9, "RI_9", MEPCORE1_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_10, "RI_10", MEPCORE1_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_11, "RI_11", MEPCORE1_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_12, "RI_12", MEPCORE1_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_13, "RI_13", MEPCORE1_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_14, "RI_14", MEPCORE1_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_15, "RI_15", MEPCORE1_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_17, "RI_17", MEPCORE1_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_20, "RI_20", MEPCORE1_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_21, "RI_21", MEPCORE1_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_22, "RI_22", MEPCORE1_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_23, "RI_23", MEPCORE1_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_24, "RI_24", MEPCORE1_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_25, "RI_25", MEPCORE1_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_26, "RI_26", MEPCORE1_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_16, "RI_16", MEPCORE1_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_18, "RI_18", MEPCORE1_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mepcore1_sem_ri_19, "RI_19", MEPCORE1_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
 
 };
 
Index: sid/component/cgen-cpu/mep/mep-cpu.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cpu.h,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-cpu.h
--- sid/component/cgen-cpu/mep/mep-cpu.h 5 Feb 2007 20:28:40 -0000 1.1
+++ sid/component/cgen-cpu/mep/mep-cpu.h 3 Feb 2009 01:53:51 -0000
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
 
 This file is part of the Red Hat simulators.
 
@@ -27,8 +27,6 @@ public:
   DI h_cr64[32];
   /* Coprocessor control registers */
   SI h_ccr[64];
-  /* flag */
-  USI h_fmax_compare_i_p;
   } hardware;
 
   void stream_cgen_hardware (std::ostream &ost) const
@@ -42,7 +40,6 @@ public:
       ost << hardware.h_cr64[i] << ' ';
     for (int i = 0; i < 64; i++)
       ost << hardware.h_ccr[i] << ' ';
-    ost << hardware.h_fmax_compare_i_p << ' ';
   }
   void destream_cgen_hardware (std::istream &ist)
   {
@@ -55,7 +52,6 @@ public:
       ist >> hardware.h_cr64[i];
     for (int i = 0; i < 64; i++)
       ist >> hardware.h_ccr[i];
-    ist >> hardware.h_fmax_compare_i_p;
   }
   // C++ register access function templates
 #define current_cpu this
@@ -81,16 +77,5 @@ public:
   inline void h_ccr_set (UINT regno, SI newval) { current_cpu->cgen_set_ccr_value (regno, newval);
  }
 
-  inline SF ext_core2_h_cr_fmax_get (UINT regno) const { return current_cpu->fmax_fr_get_handler (regno); }
-  inline void ext_core2_h_cr_fmax_set (UINT regno, SF newval) { current_cpu->fmax_fr_set_handler (regno, newval);
- }
-
-  inline USI ext_core2_h_ccr_fmax_get (UINT regno) const { return current_cpu->h_ccr_get (regno); }
-  inline void ext_core2_h_ccr_fmax_set (UINT regno, USI newval) { current_cpu->h_ccr_set (regno, newval);
- }
-
-  inline USI ext_core2_h_fmax_compare_i_p_get () const { return this->hardware.h_fmax_compare_i_p; }
-  inline void ext_core2_h_fmax_compare_i_p_set (USI newval) { this->hardware.h_fmax_compare_i_p = newval; }
-
 #undef current_cpu
 
Index: sid/component/cgen-cpu/mep/mep-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-decode.cxx,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-decode.cxx
--- sid/component/cgen-cpu/mep/mep-decode.cxx 5 Feb 2007 20:28:40 -0000 1.1
+++ sid/component/cgen-cpu/mep/mep-decode.cxx 3 Feb 2009 01:53:51 -0000
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
 
 This file is part of the Red Hat simulators.
 
@@ -23,213 +23,213 @@ using namespace mep_basic; // FIXME: nam
 mep_idesc mep_idesc::idesc_table[MEP_INSN_RI_19 + 1] =
 {
   { mep_sem_x_invalid, "X_INVALID", MEP_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 0, CONFIG_NONE } },
-  { mep_sem_sb, "SB", MEP_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sh, "SH", MEP_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sw, "SW", MEP_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lb, "LB", MEP_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lh, "LH", MEP_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lw, "LW", MEP_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lbu, "LBU", MEP_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lhu, "LHU", MEP_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_sw_sp, "SW_SP", MEP_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lw_sp, "LW_SP", MEP_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_sb_tp, "SB_TP", MEP_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sh_tp, "SH_TP", MEP_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sw_tp, "SW_TP", MEP_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lb_tp, "LB_TP", MEP_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lh_tp, "LH_TP", MEP_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lw_tp, "LW_TP", MEP_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lbu_tp, "LBU_TP", MEP_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lhu_tp, "LHU_TP", MEP_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_sb16, "SB16", MEP_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sh16, "SH16", MEP_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sw16, "SW16", MEP_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lb16, "LB16", MEP_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lh16, "LH16", MEP_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lw16, "LW16", MEP_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lbu16, "LBU16", MEP_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_lhu16, "LHU16", MEP_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_sw24, "SW24", MEP_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lw24, "LW24", MEP_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_extb, "EXTB", MEP_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_exth, "EXTH", MEP_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_extub, "EXTUB", MEP_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_extuh, "EXTUH", MEP_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ssarb, "SSARB", MEP_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_mov, "MOV", MEP_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_movi8, "MOVI8", MEP_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_movi16, "MOVI16", MEP_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_movu24, "MOVU24", MEP_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_movu16, "MOVU16", MEP_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_movh, "MOVH", MEP_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_add3, "ADD3", MEP_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_add, "ADD", MEP_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_add3i, "ADD3I", MEP_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_advck3, "ADVCK3", MEP_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sub, "SUB", MEP_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sbvck3, "SBVCK3", MEP_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_neg, "NEG", MEP_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_slt3, "SLT3", MEP_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sltu3, "SLTU3", MEP_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_slt3i, "SLT3I", MEP_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sltu3i, "SLTU3I", MEP_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sl1ad3, "SL1AD3", MEP_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sl2ad3, "SL2AD3", MEP_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_add3x, "ADD3X", MEP_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_slt3x, "SLT3X", MEP_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sltu3x, "SLTU3X", MEP_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_or, "OR", MEP_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_and, "AND", MEP_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_xor, "XOR", MEP_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_nor, "NOR", MEP_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_or3, "OR3", MEP_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_and3, "AND3", MEP_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_xor3, "XOR3", MEP_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sra, "SRA", MEP_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_srl, "SRL", MEP_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sll, "SLL", MEP_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_srai, "SRAI", MEP_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_srli, "SRLI", MEP_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_slli, "SLLI", MEP_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sll3, "SLL3", MEP_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_fsft, "FSFT", MEP_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bra, "BRA", MEP_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_beqz, "BEQZ", MEP_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bnez, "BNEZ", MEP_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_beqi, "BEQI", MEP_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bnei, "BNEI", MEP_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_blti, "BLTI", MEP_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bgei, "BGEI", MEP_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_beq, "BEQ", MEP_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bne, "BNE", MEP_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bsr12, "BSR12", MEP_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bsr24, "BSR24", MEP_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_jmp, "JMP", MEP_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_jmp24, "JMP24", MEP_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_jsr, "JSR", MEP_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ret, "RET", MEP_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_repeat, "REPEAT", MEP_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_erepeat, "EREPEAT", MEP_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_stc_lp, "STC_LP", MEP_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_stc_hi, "STC_HI", MEP_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_stc_lo, "STC_LO", MEP_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_stc, "STC", MEP_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ldc_lp, "LDC_LP", MEP_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ldc_hi, "LDC_HI", MEP_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ldc_lo, "LDC_LO", MEP_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ldc, "LDC", MEP_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
-  { mep_sem_di, "DI", MEP_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ei, "EI", MEP_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_reti, "RETI", MEP_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_halt, "HALT", MEP_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sleep, "SLEEP", MEP_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_swi, "SWI", MEP_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_break, "BREAK", MEP_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_syncm, "SYNCM", MEP_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_stcb, "STCB", MEP_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ldcb, "LDCB", MEP_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mep_sem_bsetm, "BSETM", MEP_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bclrm, "BCLRM", MEP_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bnotm, "BNOTM", MEP_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_btstm, "BTSTM", MEP_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_tas, "TAS", MEP_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_cache, "CACHE", MEP_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_mul, "MUL", MEP_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_mulu, "MULU", MEP_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_mulr, "MULR", MEP_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mep_sem_mulru, "MULRU", MEP_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mep_sem_madd, "MADD", MEP_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_maddu, "MADDU", MEP_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_maddr, "MADDR", MEP_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mep_sem_maddru, "MADDRU", MEP_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
-  { mep_sem_div, "DIV", MEP_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
-  { mep_sem_divu, "DIVU", MEP_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
-  { mep_sem_dret, "DRET", MEP_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_dbreak, "DBREAK", MEP_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ldz, "LDZ", MEP_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_abs, "ABS", MEP_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ave, "AVE", MEP_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_min, "MIN", MEP_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_max, "MAX", MEP_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_minu, "MINU", MEP_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_maxu, "MAXU", MEP_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_clip, "CLIP", MEP_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_clipu, "CLIPU", MEP_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sadd, "SADD", MEP_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ssub, "SSUB", MEP_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_saddu, "SADDU", MEP_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ssubu, "SSUBU", MEP_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_swcp, "SWCP", MEP_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lwcp, "LWCP", MEP_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_smcp, "SMCP", MEP_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lmcp, "LMCP", MEP_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_swcpi, "SWCPI", MEP_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lwcpi, "LWCPI", MEP_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_smcpi, "SMCPI", MEP_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lmcpi, "LMCPI", MEP_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_swcp16, "SWCP16", MEP_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lwcp16, "LWCP16", MEP_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_smcp16, "SMCP16", MEP_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lmcp16, "LMCP16", MEP_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sbcpa, "SBCPA", MEP_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lbcpa, "LBCPA", MEP_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_shcpa, "SHCPA", MEP_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lhcpa, "LHCPA", MEP_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_swcpa, "SWCPA", MEP_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lwcpa, "LWCPA", MEP_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_smcpa, "SMCPA", MEP_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lmcpa, "LMCPA", MEP_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sbcpm0, "SBCPM0", MEP_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lbcpm0, "LBCPM0", MEP_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_shcpm0, "SHCPM0", MEP_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lhcpm0, "LHCPM0", MEP_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_swcpm0, "SWCPM0", MEP_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lwcpm0, "LWCPM0", MEP_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_smcpm0, "SMCPM0", MEP_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lmcpm0, "LMCPM0", MEP_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sbcpm1, "SBCPM1", MEP_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lbcpm1, "LBCPM1", MEP_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_shcpm1, "SHCPM1", MEP_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lhcpm1, "LHCPM1", MEP_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_swcpm1, "SWCPM1", MEP_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lwcpm1, "LWCPM1", MEP_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_smcpm1, "SMCPM1", MEP_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_lmcpm1, "LMCPM1", MEP_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bcpeq, "BCPEQ", MEP_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bcpne, "BCPNE", MEP_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bcpat, "BCPAT", MEP_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bcpaf, "BCPAF", MEP_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_synccp, "SYNCCP", MEP_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_jsrv, "JSRV", MEP_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_bsrv, "BSRV", MEP_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_sim_syscall, "SIM_SYSCALL", MEP_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_0, "RI_0", MEP_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_1, "RI_1", MEP_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_2, "RI_2", MEP_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_3, "RI_3", MEP_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_4, "RI_4", MEP_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_5, "RI_5", MEP_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_6, "RI_6", MEP_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_7, "RI_7", MEP_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_8, "RI_8", MEP_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_9, "RI_9", MEP_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_10, "RI_10", MEP_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_11, "RI_11", MEP_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_12, "RI_12", MEP_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_13, "RI_13", MEP_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_14, "RI_14", MEP_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_15, "RI_15", MEP_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_17, "RI_17", MEP_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_20, "RI_20", MEP_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_21, "RI_21", MEP_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_22, "RI_22", MEP_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_23, "RI_23", MEP_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_24, "RI_24", MEP_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_25, "RI_25", MEP_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_26, "RI_26", MEP_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_16, "RI_16", MEP_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_18, "RI_18", MEP_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
-  { mep_sem_ri_19, "RI_19", MEP_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
+  { mep_sem_sb, "SB", MEP_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sh, "SH", MEP_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sw, "SW", MEP_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lb, "LB", MEP_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lh, "LH", MEP_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lw, "LW", MEP_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lbu, "LBU", MEP_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lhu, "LHU", MEP_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_sw_sp, "SW_SP", MEP_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lw_sp, "LW_SP", MEP_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_sb_tp, "SB_TP", MEP_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sh_tp, "SH_TP", MEP_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sw_tp, "SW_TP", MEP_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lb_tp, "LB_TP", MEP_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lh_tp, "LH_TP", MEP_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lw_tp, "LW_TP", MEP_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lbu_tp, "LBU_TP", MEP_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lhu_tp, "LHU_TP", MEP_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_sb16, "SB16", MEP_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sh16, "SH16", MEP_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sw16, "SW16", MEP_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lb16, "LB16", MEP_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lh16, "LH16", MEP_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lw16, "LW16", MEP_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lbu16, "LBU16", MEP_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_lhu16, "LHU16", MEP_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_sw24, "SW24", MEP_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lw24, "LW24", MEP_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_extb, "EXTB", MEP_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_exth, "EXTH", MEP_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_extub, "EXTUB", MEP_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_extuh, "EXTUH", MEP_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ssarb, "SSARB", MEP_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_mov, "MOV", MEP_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_movi8, "MOVI8", MEP_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_movi16, "MOVI16", MEP_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_movu24, "MOVU24", MEP_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_movu16, "MOVU16", MEP_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_movh, "MOVH", MEP_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_add3, "ADD3", MEP_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_add, "ADD", MEP_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_add3i, "ADD3I", MEP_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_advck3, "ADVCK3", MEP_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sub, "SUB", MEP_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sbvck3, "SBVCK3", MEP_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_neg, "NEG", MEP_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_slt3, "SLT3", MEP_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sltu3, "SLTU3", MEP_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_slt3i, "SLT3I", MEP_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sltu3i, "SLTU3I", MEP_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sl1ad3, "SL1AD3", MEP_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sl2ad3, "SL2AD3", MEP_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_add3x, "ADD3X", MEP_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_slt3x, "SLT3X", MEP_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sltu3x, "SLTU3X", MEP_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_or, "OR", MEP_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_and, "AND", MEP_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_xor, "XOR", MEP_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_nor, "NOR", MEP_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_or3, "OR3", MEP_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_and3, "AND3", MEP_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_xor3, "XOR3", MEP_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sra, "SRA", MEP_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_srl, "SRL", MEP_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sll, "SLL", MEP_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_srai, "SRAI", MEP_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_srli, "SRLI", MEP_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_slli, "SLLI", MEP_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sll3, "SLL3", MEP_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_fsft, "FSFT", MEP_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bra, "BRA", MEP_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_beqz, "BEQZ", MEP_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bnez, "BNEZ", MEP_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_beqi, "BEQI", MEP_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bnei, "BNEI", MEP_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_blti, "BLTI", MEP_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bgei, "BGEI", MEP_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_beq, "BEQ", MEP_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bne, "BNE", MEP_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bsr12, "BSR12", MEP_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bsr24, "BSR24", MEP_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_jmp, "JMP", MEP_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_jmp24, "JMP24", MEP_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_jsr, "JSR", MEP_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ret, "RET", MEP_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_repeat, "REPEAT", MEP_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_erepeat, "EREPEAT", MEP_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_stc_lp, "STC_LP", MEP_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_stc_hi, "STC_HI", MEP_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_stc_lo, "STC_LO", MEP_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_stc, "STC", MEP_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ldc_lp, "LDC_LP", MEP_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ldc_hi, "LDC_HI", MEP_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ldc_lo, "LDC_LO", MEP_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ldc, "LDC", MEP_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
+  { mep_sem_di, "DI", MEP_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ei, "EI", MEP_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_reti, "RETI", MEP_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_halt, "HALT", MEP_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sleep, "SLEEP", MEP_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_swi, "SWI", MEP_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_break, "BREAK", MEP_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_syncm, "SYNCM", MEP_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_stcb, "STCB", MEP_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ldcb, "LDCB", MEP_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mep_sem_bsetm, "BSETM", MEP_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bclrm, "BCLRM", MEP_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bnotm, "BNOTM", MEP_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_btstm, "BTSTM", MEP_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_tas, "TAS", MEP_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_cache, "CACHE", MEP_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_mul, "MUL", MEP_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_mulu, "MULU", MEP_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_mulr, "MULR", MEP_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mep_sem_mulru, "MULRU", MEP_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mep_sem_madd, "MADD", MEP_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_maddu, "MADDU", MEP_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_maddr, "MADDR", MEP_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mep_sem_maddru, "MADDRU", MEP_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
+  { mep_sem_div, "DIV", MEP_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
+  { mep_sem_divu, "DIVU", MEP_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
+  { mep_sem_dret, "DRET", MEP_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_dbreak, "DBREAK", MEP_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ldz, "LDZ", MEP_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_abs, "ABS", MEP_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ave, "AVE", MEP_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_min, "MIN", MEP_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_max, "MAX", MEP_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_minu, "MINU", MEP_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_maxu, "MAXU", MEP_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_clip, "CLIP", MEP_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_clipu, "CLIPU", MEP_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sadd, "SADD", MEP_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ssub, "SSUB", MEP_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_saddu, "SADDU", MEP_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ssubu, "SSUBU", MEP_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_swcp, "SWCP", MEP_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lwcp, "LWCP", MEP_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_smcp, "SMCP", MEP_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lmcp, "LMCP", MEP_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_swcpi, "SWCPI", MEP_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lwcpi, "LWCPI", MEP_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_smcpi, "SMCPI", MEP_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lmcpi, "LMCPI", MEP_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_swcp16, "SWCP16", MEP_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lwcp16, "LWCP16", MEP_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_smcp16, "SMCP16", MEP_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lmcp16, "LMCP16", MEP_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sbcpa, "SBCPA", MEP_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lbcpa, "LBCPA", MEP_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_shcpa, "SHCPA", MEP_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lhcpa, "LHCPA", MEP_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_swcpa, "SWCPA", MEP_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lwcpa, "LWCPA", MEP_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_smcpa, "SMCPA", MEP_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lmcpa, "LMCPA", MEP_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sbcpm0, "SBCPM0", MEP_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lbcpm0, "LBCPM0", MEP_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_shcpm0, "SHCPM0", MEP_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lhcpm0, "LHCPM0", MEP_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_swcpm0, "SWCPM0", MEP_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lwcpm0, "LWCPM0", MEP_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_smcpm0, "SMCPM0", MEP_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lmcpm0, "LMCPM0", MEP_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sbcpm1, "SBCPM1", MEP_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lbcpm1, "LBCPM1", MEP_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_shcpm1, "SHCPM1", MEP_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lhcpm1, "LHCPM1", MEP_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_swcpm1, "SWCPM1", MEP_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lwcpm1, "LWCPM1", MEP_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_smcpm1, "SMCPM1", MEP_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_lmcpm1, "LMCPM1", MEP_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bcpeq, "BCPEQ", MEP_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bcpne, "BCPNE", MEP_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bcpat, "BCPAT", MEP_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bcpaf, "BCPAF", MEP_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_synccp, "SYNCCP", MEP_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_jsrv, "JSRV", MEP_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_bsrv, "BSRV", MEP_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_sim_syscall, "SIM_SYSCALL", MEP_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_0, "RI_0", MEP_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_1, "RI_1", MEP_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_2, "RI_2", MEP_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_3, "RI_3", MEP_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_4, "RI_4", MEP_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_5, "RI_5", MEP_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_6, "RI_6", MEP_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_7, "RI_7", MEP_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_8, "RI_8", MEP_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_9, "RI_9", MEP_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_10, "RI_10", MEP_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_11, "RI_11", MEP_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_12, "RI_12", MEP_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_13, "RI_13", MEP_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_14, "RI_14", MEP_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_15, "RI_15", MEP_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_17, "RI_17", MEP_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_20, "RI_20", MEP_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_21, "RI_21", MEP_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_22, "RI_22", MEP_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_23, "RI_23", MEP_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_24, "RI_24", MEP_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_25, "RI_25", MEP_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_26, "RI_26", MEP_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_16, "RI_16", MEP_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_18, "RI_18", MEP_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
+  { mep_sem_ri_19, "RI_19", MEP_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
 
 };
 
Index: sid/component/cgen-cpu/mep/mep-desc.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-desc.h,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-desc.h
--- sid/component/cgen-cpu/mep/mep-desc.h 5 Feb 2007 20:28:40 -0000 1.1
+++ sid/component/cgen-cpu/mep/mep-desc.h 3 Feb 2009 01:53:51 -0000
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 2000-2005 Red Hat, Inc.
+Copyright (C) 2000-2007 Red Hat, Inc.
 
 This file is part of the Red Hat simulators.
 
@@ -26,14 +26,6 @@ typedef enum major {
  , MAJ_12, MAJ_13, MAJ_14, MAJ_15
 } MAJOR;
 
-/* Enum declaration for condition opcode enum.  */
-typedef enum fmax_cond {
-  FMAX_F, FMAX_U, FMAX_E, FMAX_UE
- , FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE
- , FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI
- , FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI
-} FMAX_COND;
-
 // Insn attribute indices.
 
 /* Enum declaration for cgen_insn attrs.  */
@@ -62,8 +54,7 @@ typedef enum mach_attr {
 
 /* Enum declaration for instruction set selection.  */
 typedef enum isa_attr {
-  ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16
- , ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX
+  ISA_MEP, ISA_EXT_CORE1, ISA_MAX
 } ISA_ATTR;
 
 /* Enum declaration for datatype to use for C intrinsics mapping.  */
@@ -75,7 +66,7 @@ typedef enum cdata_attr {
 
 /* Enum declaration for .  */
 typedef enum config_attr {
-  CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX
+  CONFIG_NONE, CONFIG_DEFAULT
 } CONFIG_ATTR;
 
 // Insn attributes.
Index: sid/component/cgen-cpu/mep/mep.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep.h,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep.h
--- sid/component/cgen-cpu/mep/mep.h 5 Feb 2007 20:28:40 -0000 1.1
+++ sid/component/cgen-cpu/mep/mep.h 3 Feb 2009 01:53:51 -0000
@@ -16,8 +16,6 @@ using namespace cgen;
 using sidutil::callback_pin;
 
 // begin-fpu-includes
-#include "fmax-fp.h"
-using sidutil::fmax_fp;
 // end-fpu-includes
 
 namespace mep
@@ -27,7 +25,6 @@ namespace mep
       // Include cgen generated elements.
 #include "mep-cpu.h"
 // begin-copro-cpu-includes
-#include "fmax-cpu.h"
 // end-copro-cpu-includes
 
     public:
Index: sid/component/families/mep/ChangeLog
===================================================================
RCS file: /cvs/src/src/sid/component/families/mep/ChangeLog,v
retrieving revision 1.2
diff -p -U3 -r1.2  sid/component/families/mep/ChangeLog
--- sid/component/families/mep/ChangeLog 31 Oct 2007 14:48:04 -0000 1.2
+++ sid/component/families/mep/ChangeLog 3 Feb 2009 01:53:51 -0000
@@ -1,3 +1,7 @@
+2009-02-02  DJ Delorie  <[hidden email]>
+
+ * mm_int.h (no_relation_component): Update to new MeP configuration.
+
 2007-10-31  Dave Brolley  <[hidden email]>
 
         * components.cxx (mepfamily_component_library): Correct DLLEXPORT
Index: sid/component/families/mep/mm_int.h
===================================================================
RCS file: /cvs/src/src/sid/component/families/mep/mm_int.h,v
retrieving revision 1.1
diff -p -U3 -r1.1  sid/component/families/mep/mm_int.h
--- sid/component/families/mep/mm_int.h 5 Feb 2007 20:28:40 -0000 1.1
+++ sid/component/families/mep/mm_int.h 3 Feb 2009 01:53:51 -0000
@@ -48,7 +48,7 @@ private:
   friend class mm_int_interface;
 
   // parameters
-  static const int max_modules = 2;
+  static const int max_modules = 1;
   static const int max_channels = 0x100 / 4;
   // Control bus.
   mm_int_interface ctrl_bus;
Index: sid/main/dynamic/ChangeLog
===================================================================
RCS file: /cvs/src/src/sid/main/dynamic/ChangeLog,v
retrieving revision 1.45
diff -p -U3 -r1.45  sid/main/dynamic/ChangeLog
--- sid/main/dynamic/ChangeLog 17 Jun 2008 18:11:51 -0000 1.45
+++ sid/main/dynamic/ChangeLog 3 Feb 2009 01:53:51 -0000
@@ -1,3 +1,8 @@
+2009-02-02  DJ Delorie  <[hidden email]>
+
+ * mepCfg.cxx (MepMemCfg): Update to new MeP configuration.
+ * mainDynamic.cxx (mk_sample): Update to new MeP configuration.
+
 2008-06-17  Dave Brolley  <[hidden email]>
 
  * mainDynamic.cxx (usage): Document --reversible.
Index: sid/main/dynamic/mainDynamic.cxx
===================================================================
RCS file: /cvs/src/src/sid/main/dynamic/mainDynamic.cxx,v
retrieving revision 1.12
diff -p -U3 -r1.12  sid/main/dynamic/mainDynamic.cxx
--- sid/main/dynamic/mainDynamic.cxx 17 Jun 2008 18:11:51 -0000 1.12
+++ sid/main/dynamic/mainDynamic.cxx 3 Feb 2009 01:53:52 -0000
@@ -48,50 +48,30 @@ mk_basic (const string name, SessionCfg
 #ifdef SIDTARGET_MEP
 /* begin-mepcfgtool-factories */
 static BoardCfg *
-mk_simple (const string name, SessionCfg *sess)
+mk_default (const string name, SessionCfg *sess)
 {
-  MepBoardCfg *b = new MepBoardCfg (name, "simple", sess);
-
-  b->set_core_type (MEP_CORE_C2);
+  MepBoardCfg *b = new MepBoardCfg (name, "default", sess);
+  b->set_core_type (MEP_CORE_C4);
   b->set_cpu ("mep-ext1");
   b->add_irq_board ();
-  b->set_core_id (1);
-  b->set_intc_channel_bitw (8);
-  b->set_intc_level (15);
-  b->set_opt_biu (64);
-  b->set_endian ("big");
-  b->set_opt_abs (false);
-  b->set_opt_ave (false);
-  b->set_opt_bit (false);
-  b->set_opt_clp (false);
-  b->set_opt_div (false);
-  b->set_opt_ldz (false);
-  b->set_opt_min (false);
-  b->set_opt_mul (false);
-  b->set_opt_sat (false);
-  b->set_opt_dsu (false);
-  b->set_opt_uci (false);
-  return b;
-}
-
-static BoardCfg *
-mk_fmax (const string name, SessionCfg *sess)
-{
-  MepBoardCfg *b = new MepBoardCfg (name, "fmax", sess);
-
-  b->set_core_type (MEP_CORE_C2);
-  b->set_cpu ("mep-ext2");
-  b->add_irq_board ();
-  b->set_core_id (2);
-  b->set_intc_channel_bitw (8);
+  b->set_imem_size (32);
+  b->set_dmem_bank_num (4);
+  b->set_dmem_size (128);
+  b->set_icache_size (16);
+  b->set_icache_way (1);
+  b->set_icache_line_size (32);
+  b->set_dcache_size (16);
+  b->set_dcache_way (1);
+  b->set_dcache_line_size (32);
+  b->set_core_id (50);
+  b->set_intc_channel_bitw (32);
   b->set_intc_level (15);
-  b->add_cop ("fmax_cop", 0);
-  b->set_cop_data_bus_width (32);
-  b->set_cop_ccr ( 0, 0x00000101);
-  b->set_cop_ccr ( 1, 0x00000000);
-  b->set_cop_ccr (15, 0x00000000);
+  b->set_icache_cwf (false);
+  b->set_dcache_cwf (false);
+  b->add_timer (4);
+  b->add_dmac (6, 64, true);
   b->set_opt_biu (64);
-  b->set_endian ("big");
+  b->set_endian ("little");
   b->set_opt_abs (true);
   b->set_opt_ave (true);
   b->set_opt_bit (true);
@@ -113,8 +93,7 @@ static boardspec boards [] = {
   {"basic", "basic cpu + memory board", & mk_basic},
 #ifdef SIDTARGET_MEP
 /* begin-mepcfgtool-boards */
-  { "simple", "MeP custom board 'simple'", & mk_simple },
-  { "fmax", "MeP custom board 'fmax'", & mk_fmax },
+  { "default", "MeP custom board 'default'", & mk_default },
 /* end-mepcfgtool-boards */
 #endif /* SIDTARGET_MEP */
 #if defined (SIDTARGET_SH) || defined (SIDTARGET_SH64)
Index: sid/main/dynamic/mepCfg.cxx
===================================================================
RCS file: /cvs/src/src/sid/main/dynamic/mepCfg.cxx,v
retrieving revision 1.3
diff -p -U3 -r1.3  sid/main/dynamic/mepCfg.cxx
--- sid/main/dynamic/mepCfg.cxx 6 Nov 2007 21:06:05 -0000 1.3
+++ sid/main/dynamic/mepCfg.cxx 3 Feb 2009 01:53:52 -0000
@@ -263,7 +263,7 @@ public:
     // begin-global-memory-regions
     mems.push_back (new MepMemRegionCfg ("shared-mem0", 0x0, 0x200000, 10, 1, false, true));
     mems.push_back (new MepMemRegionCfg ("shared-mem1", 0x800000, 0x800000, 10, 1, true, false));
-    mems.push_back (new MepMemRegionCfg ("shared-mem2", 0x80800000, 0x800000, 10, 1, false, false));
+    mems.push_back (new MepMemRegionCfg ("shared-mem2", 0x80000000, 0x800000, 10, 1, true, false));
     // end-global-memory-regions
 
     // begin-shadow-regions
@@ -1871,6 +1871,9 @@ void MepBoardCfg::configure_icache ()
 
   // Pass the appropriate peripheral regions
   // begin-icache-settings
+  if (get_module_type () == "default")
+    {
+    }
   // end-icache-settings
 
   // pass the imem/dmem space, which is always present.
@@ -1949,6 +1952,9 @@ void MepBoardCfg::configure_dcache ()
 
   // Pass the appropriate peripheral regions
   // begin-dcache-settings
+  if (get_module_type () == "default")
+    {
+    }
   // end-dcache-settings
 
   // pass the imem/dmem space, which is always present.
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Re: [mep] configuration regen

Dave Brolley-2
Hi DJ,

This looks like the results of running MeP-Integrator on a new default
config file. Correct? Are there any hand-written changes here that you
can highlight for me? Otherwise, it looks ok to me.

Dave

DJ Delorie wrote:

> Toshiba has requested a new default configuration.  This is a regen of
> affected files.  Ok to apply?
>
> Index: sid/component/cgen-cpu/ChangeLog
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/ChangeLog,v
> retrieving revision 1.81
> diff -p -U3 -r1.81  sid/component/cgen-cpu/ChangeLog
> --- sid/component/cgen-cpu/ChangeLog 5 Feb 2007 20:28:39 -0000 1.81
> +++ sid/component/cgen-cpu/ChangeLog 3 Feb 2009 01:53:50 -0000
> @@ -1,3 +1,7 @@
> +2009-02-02  DJ Delorie  <[hidden email]>
> +
> + * compCGEN.cxx: Update to new MeP configuration.
> +
>  2007-02-05  Dave Brolley  <[hidden email]>
>  
>   * Contribute the following changes:
> Index: sid/component/cgen-cpu/compCGEN.cxx
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/compCGEN.cxx,v
> retrieving revision 1.22
> diff -p -U3 -r1.22  sid/component/cgen-cpu/compCGEN.cxx
> --- sid/component/cgen-cpu/compCGEN.cxx 5 Feb 2007 20:28:39 -0000 1.22
> +++ sid/component/cgen-cpu/compCGEN.cxx 3 Feb 2009 01:53:50 -0000
> @@ -30,7 +30,6 @@ extern "C" {
>  #include "mep_basic.h"
>  // begin-mep-includes
>  #include "mep_ext1.h"
> -#include "mep_ext2.h"
>  // end-mep-includes
>  #endif
>  #if SIDTARGET_MT
> @@ -331,7 +330,6 @@ compCGENListTypes ()
>    types.push_back ("hw-cpu-mep");
>    // begin-mep-types
>    types.push_back ("hw-cpu-mep-ext1");
> -  types.push_back ("hw-cpu-mep-ext2");
>    // end-mep-types
>  #endif
>  #if SIDTARGET_MT
> @@ -383,8 +381,6 @@ compCGENCreate (const string& typeName)
>    // begin-mep-constructors
>    if (typeName == "hw-cpu-mep-ext1")
>      return new mep_ext1::mep_ext1_cpu ();
> -  if (typeName == "hw-cpu-mep-ext2")
> -    return new mep_ext2::mep_ext2_cpu ();
>    // end-mep-constructors
>  #endif
>  #if SIDTARGET_MT
> Index: sid/component/cgen-cpu/mep/ChangeLog
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/ChangeLog,v
> retrieving revision 1.2
> diff -p -U3 -r1.2  sid/component/cgen-cpu/mep/ChangeLog
> --- sid/component/cgen-cpu/mep/ChangeLog 13 Aug 2007 14:47:43 -0000 1.2
> +++ sid/component/cgen-cpu/mep/ChangeLog 3 Feb 2009 01:53:51 -0000
> @@ -1,3 +1,14 @@
> +2009-02-02  DJ Delorie  <[hidden email]>
> +
> + * Makefile.am: Update to new MeP configuration.
> + * Makefile.in: Likewise.
> + * common_model.cxx: Likewise.
> + * mep-core1-decode.cxx: Likewise.
> + * mep-cpu.h: Likewise.
> + * mep-decode.cxx: Likewise.
> + * mep-desc.h: Likewise.
> + * mep.h: Likewise.
> +
>  2007-08-13  Frank Ch. Eigler  <[hidden email]>
>  
>   * common_model.h: Change #include guard name.
> Index: sid/component/cgen-cpu/mep/Makefile.am
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/Makefile.am,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/Makefile.am
> --- sid/component/cgen-cpu/mep/Makefile.am 5 Feb 2007 20:28:39 -0000 1.1
> +++ sid/component/cgen-cpu/mep/Makefile.am 3 Feb 2009 01:53:51 -0000
> @@ -11,7 +11,7 @@ CXXFLAGS = $(TOP_CXXFLAGS) -DHAVE_CONFIG
>  
>  pkgdata_DATA = hw-cpu-mep.txt
>  
> -CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx mep-core2-decode.cxx mep-core2-sem.cxx mep-core2-model.cxx mep-cop2-16-decode.cxx mep-cop2-16-sem.cxx mep-cop2-16-model.cxx mep-cop2-32-decode.cxx mep-cop2-32-sem.cxx mep-cop2-32-model.cxx mep-cop2-48-decode.cxx mep-cop2-48-sem.cxx mep-cop2-48-model.cxx mep-cop2-64-decode.cxx mep-cop2-64-sem.cxx mep-cop2-64-model.cxx fmax-fp.cxx fmax-fpu.cxx
> +CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx
>  
>  libmep_la_SOURCES = mep.cxx common_model.cxx mep-decode.cxx mep-sem.cxx mep-model.cxx $(CPU_SOURCES)
>  libmep_la_LDFLAGS =
> @@ -57,9 +57,9 @@ CGENDEPS = ../../../../cgen/stamp-cgen \
>          $(cgendir)/sim-test.scm  $(cgendir)/sim-cpu.scm \
>          $(cgendir)/sim-model.scm $(cgendir)/sim.scm
>  
> -CPU_TARGETS = mep-core1 mep-core2 mep-cop2-16 mep-cop2-32 mep-cop2-48 mep-cop2-64
> +CPU_TARGETS = mep-core1
>  
> -CPU_LIST = mep,ext_core1,ext_core2,ext_cop2_16,ext_cop2_32,ext_cop2_48,ext_cop2_64
> +CPU_LIST = mep,ext_core1
>  
>  CGEN_TARGETS = mep-cpudesc mep-decsemdefs $(CPU_TARGETS)
>  .PHONY: $(CGEN_TARGETS)
> @@ -73,31 +73,6 @@ mep-core1:
>   mep "with-multiple-isa with-scache with-profile=fn" mep_ext1 ext_core1 $(CGEN_MACH) mepcore1 "mep-core1-" \
>   $(cgendir)/cpu/mep.cpu \
>   "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-core2:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_core2 $(CGEN_MACH) mepcore2 "mep-core2-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-16:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_16 $(CGEN_MACH) mepcop2_16 "mep-cop2-16-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-32:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_32 $(CGEN_MACH) mepcop2_32 "mep-cop2-32-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-48:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_48 $(CGEN_MACH) mepcop2_48 "mep-cop2-48-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-64:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_64 $(CGEN_MACH) mepcop2_64 "mep-cop2-64-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
>  # end-cpus
>  mep-cpudesc:
>   $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> Index: sid/component/cgen-cpu/mep/Makefile.in
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/Makefile.in,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/Makefile.in
> --- sid/component/cgen-cpu/mep/Makefile.in 5 Feb 2007 20:28:39 -0000 1.1
> +++ sid/component/cgen-cpu/mep/Makefile.in 3 Feb 2009 01:53:51 -0000
> @@ -74,13 +74,8 @@ CONFIG_CLEAN_FILES =
>  LTLIBRARIES = $(noinst_LTLIBRARIES)
>  libmep_la_DEPENDENCIES = mep-asm.lo mep-dis.lo mep-opc.lo mep-ibld.lo \
>   mep-desc.lo
> -am__objects_1 = mep-core1-decode.lo mep-core1-sem.lo \
> - mep-core1-model.lo mep-core2-decode.lo mep-core2-sem.lo \
> - mep-core2-model.lo mep-cop2-16-decode.lo mep-cop2-16-sem.lo \
> - mep-cop2-16-model.lo mep-cop2-32-decode.lo mep-cop2-32-sem.lo \
> - mep-cop2-32-model.lo mep-cop2-48-decode.lo mep-cop2-48-sem.lo \
> - mep-cop2-48-model.lo mep-cop2-64-decode.lo mep-cop2-64-sem.lo \
> - mep-cop2-64-model.lo fmax-fp.lo fmax-fpu.lo
> +am__objects_1 = \
> +mep-core1-decode.lo mep-core1-sem.lo mep-core1-model.lo
>  am_libmep_la_OBJECTS = mep.lo common_model.lo mep-decode.lo mep-sem.lo \
>   mep-model.lo $(am__objects_1)
>  libmep_la_OBJECTS = $(am_libmep_la_OBJECTS)
> @@ -241,7 +236,7 @@ noinst_LTLIBRARIES = libmep.la
>  BFDINCLUDES = -I../../../../bfd -I$(srcdir)/../../../../include
>  INCLUDES = -I$(srcdir) -I$(srcdir)/.. -I.. -I../../../include -I$(srcdir)/../../../include $(BFDINCLUDES)
>  pkgdata_DATA = hw-cpu-mep.txt
> -CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx mep-core2-decode.cxx mep-core2-sem.cxx mep-core2-model.cxx mep-cop2-16-decode.cxx mep-cop2-16-sem.cxx mep-cop2-16-model.cxx mep-cop2-32-decode.cxx mep-cop2-32-sem.cxx mep-cop2-32-model.cxx mep-cop2-48-decode.cxx mep-cop2-48-sem.cxx mep-cop2-48-model.cxx mep-cop2-64-decode.cxx mep-cop2-64-sem.cxx mep-cop2-64-model.cxx fmax-fp.cxx fmax-fpu.cxx
> +CPU_SOURCES = mep-core1-decode.cxx mep-core1-sem.cxx mep-core1-model.cxx
>  libmep_la_SOURCES = mep.cxx common_model.cxx mep-decode.cxx mep-sem.cxx mep-model.cxx $(CPU_SOURCES)
>  libmep_la_LDFLAGS =
>  libmep_la_LIBADD = mep-asm.lo mep-dis.lo mep-opc.lo mep-ibld.lo mep-desc.lo
> @@ -264,8 +259,8 @@ CGENDEPS = ../../../../cgen/stamp-cgen \
>          $(cgendir)/sim-test.scm  $(cgendir)/sim-cpu.scm \
>          $(cgendir)/sim-model.scm $(cgendir)/sim.scm
>  
> -CPU_TARGETS = mep-core1 mep-core2 mep-cop2-16 mep-cop2-32 mep-cop2-48 mep-cop2-64
> -CPU_LIST = mep,ext_core1,ext_core2,ext_cop2_16,ext_cop2_32,ext_cop2_48,ext_cop2_64
> +CPU_TARGETS = mep-core1
> +CPU_LIST = mep,ext_core1
>  CGEN_TARGETS = mep-cpudesc mep-decsemdefs $(CPU_TARGETS)
>  html_stylesheet = $(srcdir)/../../component_html.xsl
>  SUFFIXES = .xml .txt .html
> @@ -325,26 +320,9 @@ distclean-compile:
>   -rm -f *.tab.c
>  
>  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/common_model.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fmax-fp.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/fmax-fpu.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-16-decode.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-16-model.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-16-sem.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-32-decode.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-32-model.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-32-sem.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-48-decode.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-48-model.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-48-sem.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-64-decode.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-64-model.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-cop2-64-sem.Plo@am__quote@
>  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core1-decode.Plo@am__quote@
>  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core1-model.Plo@am__quote@
>  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core1-sem.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core2-decode.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core2-model.Plo@am__quote@
> -@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-core2-sem.Plo@am__quote@
>  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-decode.Plo@am__quote@
>  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-model.Plo@am__quote@
>  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mep-sem.Plo@am__quote@
> @@ -703,31 +681,6 @@ mep-core1:
>   mep "with-multiple-isa with-scache with-profile=fn" mep_ext1 ext_core1 $(CGEN_MACH) mepcore1 "mep-core1-" \
>   $(cgendir)/cpu/mep.cpu \
>   "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-core2:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_core2 $(CGEN_MACH) mepcore2 "mep-core2-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-16:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_16 $(CGEN_MACH) mepcop2_16 "mep-cop2-16-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-32:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_32 $(CGEN_MACH) mepcop2_32 "mep-cop2-32-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-48:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_48 $(CGEN_MACH) mepcop2_48 "mep-cop2-48-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
> -mep-cop2-64:
> - $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> - mep "with-multiple-isa with-scache with-profile=fn" mep_ext2 ext_cop2_64 $(CGEN_MACH) mepcop2_64 "mep-cop2-64-" \
> - $(cgendir)/cpu/mep.cpu \
> - "decode.h decode.cxx model.h model.cxx semantics.cxx defs.h"
>  # end-cpus
>  mep-cpudesc:
>   $(SHELL) ../CGEN.sh cpu-decode $(srcdir) $(cgendir) "$(CGENFLAGS)" \
> Index: sid/component/cgen-cpu/mep/common_model.cxx
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/common_model.cxx,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/common_model.cxx
> --- sid/component/cgen-cpu/mep/common_model.cxx 5 Feb 2007 20:28:40 -0000 1.1
> +++ sid/component/cgen-cpu/mep/common_model.cxx 3 Feb 2009 01:53:51 -0000
> @@ -10,14 +10,12 @@
>  #include "mep_basic.h"
>  // begin-includes
>  #include "mep_ext1.h"
> -#include "mep_ext2.h"
>  // end-includes
>  
>  using namespace cgen;
>  using namespace mep_basic;
>  // begin-namespaces
>  using namespace mep_ext1;
> -using namespace mep_ext2;
>  // end-namespaces
>  
>  // !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
> @@ -40,11 +38,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_ldcb_before (mep_basic_cpu *, const mep_idesc *, int unit_num);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_ldcb_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_ldcb_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -59,11 +52,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_divide_before (mep_basic_cpu *, const mep_idesc *, int unit_num);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_divide_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_divide_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -78,11 +66,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_multiply_before (mep_basic_cpu *, const mep_idesc *, int unit_num);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_multiply_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_multiply_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -97,11 +80,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_use_ctrl_reg_before (mep_basic_cpu *, const mep_idesc *, int unit_num, INT usereg);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_use_ctrl_reg_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_use_ctrl_reg_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, INT usereg);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -117,11 +95,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_use_gpr_before (mep_basic_cpu *, const mep_idesc *, int unit_num, INT usereg);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_use_gpr_before (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, INT usereg);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_use_gpr_before (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, INT usereg);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -144,11 +117,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_branch_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_branch_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_branch_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -166,11 +134,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_multiply_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_multiply_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_multiply_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -188,11 +151,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_stcb_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_stcb_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_stcb_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -217,11 +175,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_divide_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_divide_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_divide_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -241,11 +194,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_load_gpr_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_load_gpr_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_load_gpr_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -265,11 +213,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_ldcb_gpr_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_ldcb_gpr_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_ldcb_gpr_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced, INT loadreg);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -289,11 +232,6 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template UINT mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::model_u_mul_gpr_after (mep_basic_cpu *, const mep_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
>  template UINT mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::model_u_mul_gpr_after (mep_ext1_cpu *, const mepcore1_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
> -template UINT mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcore2_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
> -template UINT mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_16_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
> -template UINT mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_32_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
> -template UINT mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_48_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
> -template UINT mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::model_u_mul_gpr_after (mep_ext2_cpu *, const mepcop2_64_idesc *, int unit_num, unsigned long long referenced, INT resultreg);
>  // end-generated-instantiations
>  
>  template <class BASE, class CPU, class IDESC, class SCACHE>
> @@ -330,9 +268,4 @@ mep_common_model<BASE, CPU, IDESC, SCACH
>  // begin-generated-instantiations
>  template void mep_common_model<mep_mep_model,mep_basic_cpu,mep_idesc,mep_scache>::step_latency (sid::host_int_4 cycles);
>  template void mep_common_model<mepcore1_mep_model,mep_ext1_cpu,mepcore1_idesc,mepcore1_scache>::step_latency (sid::host_int_4 cycles);
> -template void mep_common_model<mepcore2_mep_model,mep_ext2_cpu,mepcore2_idesc,mepcore2_scache>::step_latency (sid::host_int_4 cycles);
> -template void mep_common_model<mepcop2_16_mep_model,mep_ext2_cpu,mepcop2_16_idesc,mepcop2_16_scache>::step_latency (sid::host_int_4 cycles);
> -template void mep_common_model<mepcop2_32_mep_model,mep_ext2_cpu,mepcop2_32_idesc,mepcop2_32_scache>::step_latency (sid::host_int_4 cycles);
> -template void mep_common_model<mepcop2_48_mep_model,mep_ext2_cpu,mepcop2_48_idesc,mepcop2_48_scache>::step_latency (sid::host_int_4 cycles);
> -template void mep_common_model<mepcop2_64_mep_model,mep_ext2_cpu,mepcop2_64_idesc,mepcop2_64_scache>::step_latency (sid::host_int_4 cycles);
>  // end-generated-instantiations
> Index: sid/component/cgen-cpu/mep/mep-core1-decode.cxx
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-core1-decode.cxx,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-core1-decode.cxx
> --- sid/component/cgen-cpu/mep/mep-core1-decode.cxx 5 Feb 2007 20:28:40 -0000 1.1
> +++ sid/component/cgen-cpu/mep/mep-core1-decode.cxx 3 Feb 2009 01:53:51 -0000
> @@ -2,7 +2,7 @@
>  
>  THIS FILE IS MACHINE GENERATED WITH CGEN.
>  
> -Copyright (C) 2000-2005 Red Hat, Inc.
> +Copyright (C) 2000-2007 Red Hat, Inc.
>  
>  This file is part of the Red Hat simulators.
>  
> @@ -23,213 +23,213 @@ using namespace mep_ext1; // FIXME: name
>  mepcore1_idesc mepcore1_idesc::idesc_table[MEPCORE1_INSN_RI_19 + 1] =
>  {
>    { mepcore1_sem_x_invalid, "X_INVALID", MEPCORE1_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x40" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sb, "SB", MEPCORE1_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sh, "SH", MEPCORE1_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sw, "SW", MEPCORE1_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lb, "LB", MEPCORE1_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lh, "LH", MEPCORE1_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lw, "LW", MEPCORE1_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lbu, "LBU", MEPCORE1_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lhu, "LHU", MEPCORE1_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_sw_sp, "SW_SP", MEPCORE1_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lw_sp, "LW_SP", MEPCORE1_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_sb_tp, "SB_TP", MEPCORE1_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sh_tp, "SH_TP", MEPCORE1_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sw_tp, "SW_TP", MEPCORE1_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lb_tp, "LB_TP", MEPCORE1_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lh_tp, "LH_TP", MEPCORE1_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lw_tp, "LW_TP", MEPCORE1_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lbu_tp, "LBU_TP", MEPCORE1_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lhu_tp, "LHU_TP", MEPCORE1_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_sb16, "SB16", MEPCORE1_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sh16, "SH16", MEPCORE1_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sw16, "SW16", MEPCORE1_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lb16, "LB16", MEPCORE1_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lh16, "LH16", MEPCORE1_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lw16, "LW16", MEPCORE1_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lbu16, "LBU16", MEPCORE1_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_lhu16, "LHU16", MEPCORE1_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_sw24, "SW24", MEPCORE1_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lw24, "LW24", MEPCORE1_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_extb, "EXTB", MEPCORE1_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_exth, "EXTH", MEPCORE1_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_extub, "EXTUB", MEPCORE1_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_extuh, "EXTUH", MEPCORE1_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ssarb, "SSARB", MEPCORE1_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_mov, "MOV", MEPCORE1_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_movi8, "MOVI8", MEPCORE1_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_movi16, "MOVI16", MEPCORE1_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_movu24, "MOVU24", MEPCORE1_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_movu16, "MOVU16", MEPCORE1_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_movh, "MOVH", MEPCORE1_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_add3, "ADD3", MEPCORE1_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_add, "ADD", MEPCORE1_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_add3i, "ADD3I", MEPCORE1_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_advck3, "ADVCK3", MEPCORE1_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sub, "SUB", MEPCORE1_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sbvck3, "SBVCK3", MEPCORE1_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_neg, "NEG", MEPCORE1_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_slt3, "SLT3", MEPCORE1_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sltu3, "SLTU3", MEPCORE1_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_slt3i, "SLT3I", MEPCORE1_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sltu3i, "SLTU3I", MEPCORE1_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sl1ad3, "SL1AD3", MEPCORE1_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sl2ad3, "SL2AD3", MEPCORE1_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_add3x, "ADD3X", MEPCORE1_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_slt3x, "SLT3X", MEPCORE1_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sltu3x, "SLTU3X", MEPCORE1_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_or, "OR", MEPCORE1_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_and, "AND", MEPCORE1_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_xor, "XOR", MEPCORE1_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_nor, "NOR", MEPCORE1_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_or3, "OR3", MEPCORE1_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_and3, "AND3", MEPCORE1_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_xor3, "XOR3", MEPCORE1_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sra, "SRA", MEPCORE1_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_srl, "SRL", MEPCORE1_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sll, "SLL", MEPCORE1_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_srai, "SRAI", MEPCORE1_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_srli, "SRLI", MEPCORE1_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_slli, "SLLI", MEPCORE1_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sll3, "SLL3", MEPCORE1_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_fsft, "FSFT", MEPCORE1_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bra, "BRA", MEPCORE1_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_beqz, "BEQZ", MEPCORE1_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bnez, "BNEZ", MEPCORE1_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_beqi, "BEQI", MEPCORE1_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bnei, "BNEI", MEPCORE1_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_blti, "BLTI", MEPCORE1_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bgei, "BGEI", MEPCORE1_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_beq, "BEQ", MEPCORE1_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bne, "BNE", MEPCORE1_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bsr12, "BSR12", MEPCORE1_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bsr24, "BSR24", MEPCORE1_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_jmp, "JMP", MEPCORE1_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_jmp24, "JMP24", MEPCORE1_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_jsr, "JSR", MEPCORE1_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ret, "RET", MEPCORE1_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_repeat, "REPEAT", MEPCORE1_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_erepeat, "EREPEAT", MEPCORE1_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_stc_lp, "STC_LP", MEPCORE1_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_stc_hi, "STC_HI", MEPCORE1_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_stc_lo, "STC_LO", MEPCORE1_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_stc, "STC", MEPCORE1_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ldc_lp, "LDC_LP", MEPCORE1_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ldc_hi, "LDC_HI", MEPCORE1_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ldc_lo, "LDC_LO", MEPCORE1_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ldc, "LDC", MEPCORE1_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mepcore1_sem_di, "DI", MEPCORE1_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ei, "EI", MEPCORE1_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_reti, "RETI", MEPCORE1_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_halt, "HALT", MEPCORE1_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sleep, "SLEEP", MEPCORE1_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_swi, "SWI", MEPCORE1_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_break, "BREAK", MEPCORE1_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_syncm, "SYNCM", MEPCORE1_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_stcb, "STCB", MEPCORE1_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ldcb, "LDCB", MEPCORE1_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mepcore1_sem_bsetm, "BSETM", MEPCORE1_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bclrm, "BCLRM", MEPCORE1_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bnotm, "BNOTM", MEPCORE1_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_btstm, "BTSTM", MEPCORE1_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_tas, "TAS", MEPCORE1_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_cache, "CACHE", MEPCORE1_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_mul, "MUL", MEPCORE1_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_mulu, "MULU", MEPCORE1_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_mulr, "MULR", MEPCORE1_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mepcore1_sem_mulru, "MULRU", MEPCORE1_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mepcore1_sem_madd, "MADD", MEPCORE1_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_maddu, "MADDU", MEPCORE1_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_maddr, "MADDR", MEPCORE1_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mepcore1_sem_maddru, "MADDRU", MEPCORE1_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mepcore1_sem_div, "DIV", MEPCORE1_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
> -  { mepcore1_sem_divu, "DIVU", MEPCORE1_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
> -  { mepcore1_sem_dret, "DRET", MEPCORE1_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_dbreak, "DBREAK", MEPCORE1_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ldz, "LDZ", MEPCORE1_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_abs, "ABS", MEPCORE1_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ave, "AVE", MEPCORE1_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_min, "MIN", MEPCORE1_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_max, "MAX", MEPCORE1_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_minu, "MINU", MEPCORE1_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_maxu, "MAXU", MEPCORE1_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_clip, "CLIP", MEPCORE1_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_clipu, "CLIPU", MEPCORE1_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sadd, "SADD", MEPCORE1_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ssub, "SSUB", MEPCORE1_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_saddu, "SADDU", MEPCORE1_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ssubu, "SSUBU", MEPCORE1_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_swcp, "SWCP", MEPCORE1_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lwcp, "LWCP", MEPCORE1_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_smcp, "SMCP", MEPCORE1_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lmcp, "LMCP", MEPCORE1_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_swcpi, "SWCPI", MEPCORE1_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lwcpi, "LWCPI", MEPCORE1_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_smcpi, "SMCPI", MEPCORE1_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lmcpi, "LMCPI", MEPCORE1_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_swcp16, "SWCP16", MEPCORE1_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lwcp16, "LWCP16", MEPCORE1_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_smcp16, "SMCP16", MEPCORE1_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lmcp16, "LMCP16", MEPCORE1_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sbcpa, "SBCPA", MEPCORE1_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lbcpa, "LBCPA", MEPCORE1_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_shcpa, "SHCPA", MEPCORE1_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lhcpa, "LHCPA", MEPCORE1_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_swcpa, "SWCPA", MEPCORE1_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lwcpa, "LWCPA", MEPCORE1_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_smcpa, "SMCPA", MEPCORE1_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lmcpa, "LMCPA", MEPCORE1_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sbcpm0, "SBCPM0", MEPCORE1_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lbcpm0, "LBCPM0", MEPCORE1_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_shcpm0, "SHCPM0", MEPCORE1_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lhcpm0, "LHCPM0", MEPCORE1_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_swcpm0, "SWCPM0", MEPCORE1_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lwcpm0, "LWCPM0", MEPCORE1_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_smcpm0, "SMCPM0", MEPCORE1_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lmcpm0, "LMCPM0", MEPCORE1_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sbcpm1, "SBCPM1", MEPCORE1_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lbcpm1, "LBCPM1", MEPCORE1_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_shcpm1, "SHCPM1", MEPCORE1_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lhcpm1, "LHCPM1", MEPCORE1_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_swcpm1, "SWCPM1", MEPCORE1_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lwcpm1, "LWCPM1", MEPCORE1_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_smcpm1, "SMCPM1", MEPCORE1_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_lmcpm1, "LMCPM1", MEPCORE1_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bcpeq, "BCPEQ", MEPCORE1_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bcpne, "BCPNE", MEPCORE1_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bcpat, "BCPAT", MEPCORE1_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bcpaf, "BCPAF", MEPCORE1_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_synccp, "SYNCCP", MEPCORE1_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_jsrv, "JSRV", MEPCORE1_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_bsrv, "BSRV", MEPCORE1_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_sim_syscall, "SIM_SYSCALL", MEPCORE1_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_0, "RI_0", MEPCORE1_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_1, "RI_1", MEPCORE1_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_2, "RI_2", MEPCORE1_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_3, "RI_3", MEPCORE1_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_4, "RI_4", MEPCORE1_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_5, "RI_5", MEPCORE1_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_6, "RI_6", MEPCORE1_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_7, "RI_7", MEPCORE1_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_8, "RI_8", MEPCORE1_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_9, "RI_9", MEPCORE1_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_10, "RI_10", MEPCORE1_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_11, "RI_11", MEPCORE1_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_12, "RI_12", MEPCORE1_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_13, "RI_13", MEPCORE1_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_14, "RI_14", MEPCORE1_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_15, "RI_15", MEPCORE1_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_17, "RI_17", MEPCORE1_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_20, "RI_20", MEPCORE1_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_21, "RI_21", MEPCORE1_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_22, "RI_22", MEPCORE1_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_23, "RI_23", MEPCORE1_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_24, "RI_24", MEPCORE1_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_25, "RI_25", MEPCORE1_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_26, "RI_26", MEPCORE1_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_16, "RI_16", MEPCORE1_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_18, "RI_18", MEPCORE1_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mepcore1_sem_ri_19, "RI_19", MEPCORE1_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sb, "SB", MEPCORE1_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sh, "SH", MEPCORE1_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sw, "SW", MEPCORE1_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lb, "LB", MEPCORE1_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lh, "LH", MEPCORE1_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lw, "LW", MEPCORE1_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lbu, "LBU", MEPCORE1_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lhu, "LHU", MEPCORE1_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_sw_sp, "SW_SP", MEPCORE1_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lw_sp, "LW_SP", MEPCORE1_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_sb_tp, "SB_TP", MEPCORE1_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sh_tp, "SH_TP", MEPCORE1_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sw_tp, "SW_TP", MEPCORE1_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lb_tp, "LB_TP", MEPCORE1_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lh_tp, "LH_TP", MEPCORE1_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lw_tp, "LW_TP", MEPCORE1_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lbu_tp, "LBU_TP", MEPCORE1_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lhu_tp, "LHU_TP", MEPCORE1_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_sb16, "SB16", MEPCORE1_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sh16, "SH16", MEPCORE1_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sw16, "SW16", MEPCORE1_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lb16, "LB16", MEPCORE1_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lh16, "LH16", MEPCORE1_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lw16, "LW16", MEPCORE1_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lbu16, "LBU16", MEPCORE1_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_lhu16, "LHU16", MEPCORE1_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_sw24, "SW24", MEPCORE1_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lw24, "LW24", MEPCORE1_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_extb, "EXTB", MEPCORE1_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_exth, "EXTH", MEPCORE1_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_extub, "EXTUB", MEPCORE1_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_extuh, "EXTUH", MEPCORE1_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ssarb, "SSARB", MEPCORE1_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_mov, "MOV", MEPCORE1_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_movi8, "MOVI8", MEPCORE1_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_movi16, "MOVI16", MEPCORE1_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_movu24, "MOVU24", MEPCORE1_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_movu16, "MOVU16", MEPCORE1_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_movh, "MOVH", MEPCORE1_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_add3, "ADD3", MEPCORE1_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_add, "ADD", MEPCORE1_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_add3i, "ADD3I", MEPCORE1_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_advck3, "ADVCK3", MEPCORE1_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sub, "SUB", MEPCORE1_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sbvck3, "SBVCK3", MEPCORE1_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_neg, "NEG", MEPCORE1_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_slt3, "SLT3", MEPCORE1_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sltu3, "SLTU3", MEPCORE1_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_slt3i, "SLT3I", MEPCORE1_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sltu3i, "SLTU3I", MEPCORE1_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sl1ad3, "SL1AD3", MEPCORE1_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sl2ad3, "SL2AD3", MEPCORE1_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_add3x, "ADD3X", MEPCORE1_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_slt3x, "SLT3X", MEPCORE1_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sltu3x, "SLTU3X", MEPCORE1_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_or, "OR", MEPCORE1_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_and, "AND", MEPCORE1_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_xor, "XOR", MEPCORE1_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_nor, "NOR", MEPCORE1_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_or3, "OR3", MEPCORE1_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_and3, "AND3", MEPCORE1_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_xor3, "XOR3", MEPCORE1_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sra, "SRA", MEPCORE1_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_srl, "SRL", MEPCORE1_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sll, "SLL", MEPCORE1_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_srai, "SRAI", MEPCORE1_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_srli, "SRLI", MEPCORE1_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_slli, "SLLI", MEPCORE1_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sll3, "SLL3", MEPCORE1_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_fsft, "FSFT", MEPCORE1_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bra, "BRA", MEPCORE1_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_beqz, "BEQZ", MEPCORE1_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bnez, "BNEZ", MEPCORE1_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_beqi, "BEQI", MEPCORE1_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bnei, "BNEI", MEPCORE1_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_blti, "BLTI", MEPCORE1_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bgei, "BGEI", MEPCORE1_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_beq, "BEQ", MEPCORE1_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bne, "BNE", MEPCORE1_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bsr12, "BSR12", MEPCORE1_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bsr24, "BSR24", MEPCORE1_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_jmp, "JMP", MEPCORE1_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_jmp24, "JMP24", MEPCORE1_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_jsr, "JSR", MEPCORE1_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ret, "RET", MEPCORE1_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_repeat, "REPEAT", MEPCORE1_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_erepeat, "EREPEAT", MEPCORE1_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_stc_lp, "STC_LP", MEPCORE1_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_stc_hi, "STC_HI", MEPCORE1_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_stc_lo, "STC_LO", MEPCORE1_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_stc, "STC", MEPCORE1_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ldc_lp, "LDC_LP", MEPCORE1_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ldc_hi, "LDC_HI", MEPCORE1_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ldc_lo, "LDC_LO", MEPCORE1_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ldc, "LDC", MEPCORE1_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mepcore1_sem_di, "DI", MEPCORE1_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ei, "EI", MEPCORE1_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_reti, "RETI", MEPCORE1_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_halt, "HALT", MEPCORE1_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sleep, "SLEEP", MEPCORE1_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_swi, "SWI", MEPCORE1_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_break, "BREAK", MEPCORE1_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_syncm, "SYNCM", MEPCORE1_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_stcb, "STCB", MEPCORE1_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ldcb, "LDCB", MEPCORE1_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mepcore1_sem_bsetm, "BSETM", MEPCORE1_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bclrm, "BCLRM", MEPCORE1_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bnotm, "BNOTM", MEPCORE1_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_btstm, "BTSTM", MEPCORE1_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_tas, "TAS", MEPCORE1_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_cache, "CACHE", MEPCORE1_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_mul, "MUL", MEPCORE1_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_mulu, "MULU", MEPCORE1_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_mulr, "MULR", MEPCORE1_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mepcore1_sem_mulru, "MULRU", MEPCORE1_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mepcore1_sem_madd, "MADD", MEPCORE1_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_maddu, "MADDU", MEPCORE1_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_maddr, "MADDR", MEPCORE1_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mepcore1_sem_maddru, "MADDRU", MEPCORE1_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mepcore1_sem_div, "DIV", MEPCORE1_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
> +  { mepcore1_sem_divu, "DIVU", MEPCORE1_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
> +  { mepcore1_sem_dret, "DRET", MEPCORE1_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_dbreak, "DBREAK", MEPCORE1_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ldz, "LDZ", MEPCORE1_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_abs, "ABS", MEPCORE1_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ave, "AVE", MEPCORE1_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_min, "MIN", MEPCORE1_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_max, "MAX", MEPCORE1_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_minu, "MINU", MEPCORE1_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_maxu, "MAXU", MEPCORE1_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_clip, "CLIP", MEPCORE1_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_clipu, "CLIPU", MEPCORE1_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sadd, "SADD", MEPCORE1_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ssub, "SSUB", MEPCORE1_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_saddu, "SADDU", MEPCORE1_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ssubu, "SSUBU", MEPCORE1_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_swcp, "SWCP", MEPCORE1_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lwcp, "LWCP", MEPCORE1_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_smcp, "SMCP", MEPCORE1_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lmcp, "LMCP", MEPCORE1_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_swcpi, "SWCPI", MEPCORE1_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lwcpi, "LWCPI", MEPCORE1_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_smcpi, "SMCPI", MEPCORE1_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lmcpi, "LMCPI", MEPCORE1_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_swcp16, "SWCP16", MEPCORE1_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lwcp16, "LWCP16", MEPCORE1_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_smcp16, "SMCP16", MEPCORE1_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lmcp16, "LMCP16", MEPCORE1_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sbcpa, "SBCPA", MEPCORE1_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lbcpa, "LBCPA", MEPCORE1_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_shcpa, "SHCPA", MEPCORE1_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lhcpa, "LHCPA", MEPCORE1_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_swcpa, "SWCPA", MEPCORE1_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lwcpa, "LWCPA", MEPCORE1_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_smcpa, "SMCPA", MEPCORE1_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lmcpa, "LMCPA", MEPCORE1_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sbcpm0, "SBCPM0", MEPCORE1_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lbcpm0, "LBCPM0", MEPCORE1_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_shcpm0, "SHCPM0", MEPCORE1_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lhcpm0, "LHCPM0", MEPCORE1_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_swcpm0, "SWCPM0", MEPCORE1_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lwcpm0, "LWCPM0", MEPCORE1_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_smcpm0, "SMCPM0", MEPCORE1_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lmcpm0, "LMCPM0", MEPCORE1_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sbcpm1, "SBCPM1", MEPCORE1_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lbcpm1, "LBCPM1", MEPCORE1_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_shcpm1, "SHCPM1", MEPCORE1_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lhcpm1, "LHCPM1", MEPCORE1_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_swcpm1, "SWCPM1", MEPCORE1_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lwcpm1, "LWCPM1", MEPCORE1_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_smcpm1, "SMCPM1", MEPCORE1_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_lmcpm1, "LMCPM1", MEPCORE1_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bcpeq, "BCPEQ", MEPCORE1_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bcpne, "BCPNE", MEPCORE1_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bcpat, "BCPAT", MEPCORE1_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bcpaf, "BCPAF", MEPCORE1_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_synccp, "SYNCCP", MEPCORE1_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_jsrv, "JSRV", MEPCORE1_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_bsrv, "BSRV", MEPCORE1_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_sim_syscall, "SIM_SYSCALL", MEPCORE1_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_0, "RI_0", MEPCORE1_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_1, "RI_1", MEPCORE1_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_2, "RI_2", MEPCORE1_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_3, "RI_3", MEPCORE1_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_4, "RI_4", MEPCORE1_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_5, "RI_5", MEPCORE1_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_6, "RI_6", MEPCORE1_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_7, "RI_7", MEPCORE1_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_8, "RI_8", MEPCORE1_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_9, "RI_9", MEPCORE1_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_10, "RI_10", MEPCORE1_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_11, "RI_11", MEPCORE1_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_12, "RI_12", MEPCORE1_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_13, "RI_13", MEPCORE1_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_14, "RI_14", MEPCORE1_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_15, "RI_15", MEPCORE1_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_17, "RI_17", MEPCORE1_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_20, "RI_20", MEPCORE1_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_21, "RI_21", MEPCORE1_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_22, "RI_22", MEPCORE1_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_23, "RI_23", MEPCORE1_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_24, "RI_24", MEPCORE1_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_25, "RI_25", MEPCORE1_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_26, "RI_26", MEPCORE1_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_16, "RI_16", MEPCORE1_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_18, "RI_18", MEPCORE1_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mepcore1_sem_ri_19, "RI_19", MEPCORE1_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
>  
>  };
>  
> Index: sid/component/cgen-cpu/mep/mep-cpu.h
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cpu.h,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-cpu.h
> --- sid/component/cgen-cpu/mep/mep-cpu.h 5 Feb 2007 20:28:40 -0000 1.1
> +++ sid/component/cgen-cpu/mep/mep-cpu.h 3 Feb 2009 01:53:51 -0000
> @@ -2,7 +2,7 @@
>  
>  THIS FILE IS MACHINE GENERATED WITH CGEN.
>  
> -Copyright (C) 2000-2005 Red Hat, Inc.
> +Copyright (C) 2000-2007 Red Hat, Inc.
>  
>  This file is part of the Red Hat simulators.
>  
> @@ -27,8 +27,6 @@ public:
>    DI h_cr64[32];
>    /* Coprocessor control registers */
>    SI h_ccr[64];
> -  /* flag */
> -  USI h_fmax_compare_i_p;
>    } hardware;
>  
>    void stream_cgen_hardware (std::ostream &ost) const
> @@ -42,7 +40,6 @@ public:
>        ost << hardware.h_cr64[i] << ' ';
>      for (int i = 0; i < 64; i++)
>        ost << hardware.h_ccr[i] << ' ';
> -    ost << hardware.h_fmax_compare_i_p << ' ';
>    }
>    void destream_cgen_hardware (std::istream &ist)
>    {
> @@ -55,7 +52,6 @@ public:
>        ist >> hardware.h_cr64[i];
>      for (int i = 0; i < 64; i++)
>        ist >> hardware.h_ccr[i];
> -    ist >> hardware.h_fmax_compare_i_p;
>    }
>    // C++ register access function templates
>  #define current_cpu this
> @@ -81,16 +77,5 @@ public:
>    inline void h_ccr_set (UINT regno, SI newval) { current_cpu->cgen_set_ccr_value (regno, newval);
>   }
>  
> -  inline SF ext_core2_h_cr_fmax_get (UINT regno) const { return current_cpu->fmax_fr_get_handler (regno); }
> -  inline void ext_core2_h_cr_fmax_set (UINT regno, SF newval) { current_cpu->fmax_fr_set_handler (regno, newval);
> - }
> -
> -  inline USI ext_core2_h_ccr_fmax_get (UINT regno) const { return current_cpu->h_ccr_get (regno); }
> -  inline void ext_core2_h_ccr_fmax_set (UINT regno, USI newval) { current_cpu->h_ccr_set (regno, newval);
> - }
> -
> -  inline USI ext_core2_h_fmax_compare_i_p_get () const { return this->hardware.h_fmax_compare_i_p; }
> -  inline void ext_core2_h_fmax_compare_i_p_set (USI newval) { this->hardware.h_fmax_compare_i_p = newval; }
> -
>  #undef current_cpu
>  
> Index: sid/component/cgen-cpu/mep/mep-decode.cxx
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-decode.cxx,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-decode.cxx
> --- sid/component/cgen-cpu/mep/mep-decode.cxx 5 Feb 2007 20:28:40 -0000 1.1
> +++ sid/component/cgen-cpu/mep/mep-decode.cxx 3 Feb 2009 01:53:51 -0000
> @@ -2,7 +2,7 @@
>  
>  THIS FILE IS MACHINE GENERATED WITH CGEN.
>  
> -Copyright (C) 2000-2005 Red Hat, Inc.
> +Copyright (C) 2000-2007 Red Hat, Inc.
>  
>  This file is part of the Red Hat simulators.
>  
> @@ -23,213 +23,213 @@ using namespace mep_basic; // FIXME: nam
>  mep_idesc mep_idesc::idesc_table[MEP_INSN_RI_19 + 1] =
>  {
>    { mep_sem_x_invalid, "X_INVALID", MEP_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 0, CONFIG_NONE } },
> -  { mep_sem_sb, "SB", MEP_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sh, "SH", MEP_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sw, "SW", MEP_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lb, "LB", MEP_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lh, "LH", MEP_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lw, "LW", MEP_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lbu, "LBU", MEP_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lhu, "LHU", MEP_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_sw_sp, "SW_SP", MEP_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lw_sp, "LW_SP", MEP_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_sb_tp, "SB_TP", MEP_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sh_tp, "SH_TP", MEP_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sw_tp, "SW_TP", MEP_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lb_tp, "LB_TP", MEP_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lh_tp, "LH_TP", MEP_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lw_tp, "LW_TP", MEP_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lbu_tp, "LBU_TP", MEP_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lhu_tp, "LHU_TP", MEP_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_sb16, "SB16", MEP_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sh16, "SH16", MEP_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sw16, "SW16", MEP_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lb16, "LB16", MEP_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lh16, "LH16", MEP_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lw16, "LW16", MEP_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lbu16, "LBU16", MEP_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_lhu16, "LHU16", MEP_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_sw24, "SW24", MEP_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lw24, "LW24", MEP_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_extb, "EXTB", MEP_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_exth, "EXTH", MEP_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_extub, "EXTUB", MEP_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_extuh, "EXTUH", MEP_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ssarb, "SSARB", MEP_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_mov, "MOV", MEP_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_movi8, "MOVI8", MEP_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_movi16, "MOVI16", MEP_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_movu24, "MOVU24", MEP_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_movu16, "MOVU16", MEP_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_movh, "MOVH", MEP_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_add3, "ADD3", MEP_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_add, "ADD", MEP_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_add3i, "ADD3I", MEP_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_advck3, "ADVCK3", MEP_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sub, "SUB", MEP_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sbvck3, "SBVCK3", MEP_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_neg, "NEG", MEP_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_slt3, "SLT3", MEP_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sltu3, "SLTU3", MEP_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_slt3i, "SLT3I", MEP_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sltu3i, "SLTU3I", MEP_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sl1ad3, "SL1AD3", MEP_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sl2ad3, "SL2AD3", MEP_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_add3x, "ADD3X", MEP_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_slt3x, "SLT3X", MEP_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sltu3x, "SLTU3X", MEP_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_or, "OR", MEP_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_and, "AND", MEP_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_xor, "XOR", MEP_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_nor, "NOR", MEP_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_or3, "OR3", MEP_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_and3, "AND3", MEP_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_xor3, "XOR3", MEP_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sra, "SRA", MEP_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_srl, "SRL", MEP_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sll, "SLL", MEP_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_srai, "SRAI", MEP_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_srli, "SRLI", MEP_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_slli, "SLLI", MEP_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sll3, "SLL3", MEP_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_fsft, "FSFT", MEP_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bra, "BRA", MEP_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_beqz, "BEQZ", MEP_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bnez, "BNEZ", MEP_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_beqi, "BEQI", MEP_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bnei, "BNEI", MEP_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_blti, "BLTI", MEP_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bgei, "BGEI", MEP_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_beq, "BEQ", MEP_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bne, "BNE", MEP_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bsr12, "BSR12", MEP_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bsr24, "BSR24", MEP_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_jmp, "JMP", MEP_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_jmp24, "JMP24", MEP_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_jsr, "JSR", MEP_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ret, "RET", MEP_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_repeat, "REPEAT", MEP_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_erepeat, "EREPEAT", MEP_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_stc_lp, "STC_LP", MEP_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_stc_hi, "STC_HI", MEP_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_stc_lo, "STC_LO", MEP_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_stc, "STC", MEP_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ldc_lp, "LDC_LP", MEP_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ldc_hi, "LDC_HI", MEP_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ldc_lo, "LDC_LO", MEP_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ldc, "LDC", MEP_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 2, CONFIG_NONE } },
> -  { mep_sem_di, "DI", MEP_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ei, "EI", MEP_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_reti, "RETI", MEP_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_halt, "HALT", MEP_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sleep, "SLEEP", MEP_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_swi, "SWI", MEP_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_break, "BREAK", MEP_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_syncm, "SYNCM", MEP_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_stcb, "STCB", MEP_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ldcb, "LDCB", MEP_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mep_sem_bsetm, "BSETM", MEP_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bclrm, "BCLRM", MEP_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bnotm, "BNOTM", MEP_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_btstm, "BTSTM", MEP_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_tas, "TAS", MEP_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_cache, "CACHE", MEP_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_mul, "MUL", MEP_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_mulu, "MULU", MEP_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_mulr, "MULR", MEP_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mep_sem_mulru, "MULRU", MEP_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mep_sem_madd, "MADD", MEP_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_maddu, "MADDU", MEP_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_maddr, "MADDR", MEP_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mep_sem_maddru, "MADDRU", MEP_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 3, CONFIG_NONE } },
> -  { mep_sem_div, "DIV", MEP_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
> -  { mep_sem_divu, "DIVU", MEP_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 34, CONFIG_NONE } },
> -  { mep_sem_dret, "DRET", MEP_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_dbreak, "DBREAK", MEP_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ldz, "LDZ", MEP_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_abs, "ABS", MEP_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ave, "AVE", MEP_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_min, "MIN", MEP_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_max, "MAX", MEP_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_minu, "MINU", MEP_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_maxu, "MAXU", MEP_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_clip, "CLIP", MEP_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_clipu, "CLIPU", MEP_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sadd, "SADD", MEP_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ssub, "SSUB", MEP_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_saddu, "SADDU", MEP_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ssubu, "SSUBU", MEP_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_swcp, "SWCP", MEP_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lwcp, "LWCP", MEP_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_smcp, "SMCP", MEP_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lmcp, "LMCP", MEP_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_swcpi, "SWCPI", MEP_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lwcpi, "LWCPI", MEP_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_smcpi, "SMCPI", MEP_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lmcpi, "LMCPI", MEP_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_swcp16, "SWCP16", MEP_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lwcp16, "LWCP16", MEP_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_smcp16, "SMCP16", MEP_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lmcp16, "LMCP16", MEP_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sbcpa, "SBCPA", MEP_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lbcpa, "LBCPA", MEP_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_shcpa, "SHCPA", MEP_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lhcpa, "LHCPA", MEP_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_swcpa, "SWCPA", MEP_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lwcpa, "LWCPA", MEP_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_smcpa, "SMCPA", MEP_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lmcpa, "LMCPA", MEP_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sbcpm0, "SBCPM0", MEP_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lbcpm0, "LBCPM0", MEP_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_shcpm0, "SHCPM0", MEP_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lhcpm0, "LHCPM0", MEP_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_swcpm0, "SWCPM0", MEP_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lwcpm0, "LWCPM0", MEP_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_smcpm0, "SMCPM0", MEP_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lmcpm0, "LMCPM0", MEP_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sbcpm1, "SBCPM1", MEP_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lbcpm1, "LBCPM1", MEP_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_shcpm1, "SHCPM1", MEP_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lhcpm1, "LHCPM1", MEP_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_swcpm1, "SWCPM1", MEP_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lwcpm1, "LWCPM1", MEP_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_smcpm1, "SMCPM1", MEP_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_lmcpm1, "LMCPM1", MEP_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bcpeq, "BCPEQ", MEP_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bcpne, "BCPNE", MEP_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bcpat, "BCPAT", MEP_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bcpaf, "BCPAF", MEP_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_synccp, "SYNCCP", MEP_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_jsrv, "JSRV", MEP_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_bsrv, "BSRV", MEP_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_sim_syscall, "SIM_SYSCALL", MEP_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_0, "RI_0", MEP_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_1, "RI_1", MEP_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_2, "RI_2", MEP_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_3, "RI_3", MEP_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_4, "RI_4", MEP_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_5, "RI_5", MEP_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_6, "RI_6", MEP_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_7, "RI_7", MEP_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_8, "RI_8", MEP_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_9, "RI_9", MEP_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_10, "RI_10", MEP_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_11, "RI_11", MEP_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_12, "RI_12", MEP_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_13, "RI_13", MEP_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_14, "RI_14", MEP_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_15, "RI_15", MEP_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_17, "RI_17", MEP_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_20, "RI_20", MEP_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_21, "RI_21", MEP_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_22, "RI_22", MEP_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_23, "RI_23", MEP_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_24, "RI_24", MEP_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_25, "RI_25", MEP_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_26, "RI_26", MEP_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_16, "RI_16", MEP_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_18, "RI_18", MEP_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> -  { mep_sem_ri_19, "RI_19", MEP_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xe0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sb, "SB", MEP_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sh, "SH", MEP_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sw, "SW", MEP_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lb, "LB", MEP_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lh, "LH", MEP_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lw, "LW", MEP_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lbu, "LBU", MEP_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lhu, "LHU", MEP_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_sw_sp, "SW_SP", MEP_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lw_sp, "LW_SP", MEP_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_sb_tp, "SB_TP", MEP_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sh_tp, "SH_TP", MEP_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sw_tp, "SW_TP", MEP_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lb_tp, "LB_TP", MEP_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lh_tp, "LH_TP", MEP_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lw_tp, "LW_TP", MEP_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lbu_tp, "LBU_TP", MEP_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lhu_tp, "LHU_TP", MEP_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_sb16, "SB16", MEP_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sh16, "SH16", MEP_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sw16, "SW16", MEP_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lb16, "LB16", MEP_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lh16, "LH16", MEP_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lw16, "LW16", MEP_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lbu16, "LBU16", MEP_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_lhu16, "LHU16", MEP_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_sw24, "SW24", MEP_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lw24, "LW24", MEP_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_extb, "EXTB", MEP_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_exth, "EXTH", MEP_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_extub, "EXTUB", MEP_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_extuh, "EXTUH", MEP_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ssarb, "SSARB", MEP_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_mov, "MOV", MEP_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_movi8, "MOVI8", MEP_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_movi16, "MOVI16", MEP_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_movu24, "MOVU24", MEP_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_movu16, "MOVU16", MEP_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_movh, "MOVH", MEP_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_add3, "ADD3", MEP_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_add, "ADD", MEP_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_add3i, "ADD3I", MEP_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_advck3, "ADVCK3", MEP_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sub, "SUB", MEP_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sbvck3, "SBVCK3", MEP_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_neg, "NEG", MEP_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_slt3, "SLT3", MEP_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sltu3, "SLTU3", MEP_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_slt3i, "SLT3I", MEP_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sltu3i, "SLTU3I", MEP_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sl1ad3, "SL1AD3", MEP_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sl2ad3, "SL2AD3", MEP_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_add3x, "ADD3X", MEP_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_slt3x, "SLT3X", MEP_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sltu3x, "SLTU3X", MEP_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_or, "OR", MEP_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_and, "AND", MEP_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_xor, "XOR", MEP_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_nor, "NOR", MEP_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_or3, "OR3", MEP_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_and3, "AND3", MEP_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_xor3, "XOR3", MEP_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sra, "SRA", MEP_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_srl, "SRL", MEP_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sll, "SLL", MEP_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_srai, "SRAI", MEP_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_srli, "SRLI", MEP_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_slli, "SLLI", MEP_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sll3, "SLL3", MEP_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_fsft, "FSFT", MEP_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bra, "BRA", MEP_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_beqz, "BEQZ", MEP_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bnez, "BNEZ", MEP_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_beqi, "BEQI", MEP_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bnei, "BNEI", MEP_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_blti, "BLTI", MEP_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bgei, "BGEI", MEP_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_beq, "BEQ", MEP_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bne, "BNE", MEP_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bsr12, "BSR12", MEP_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bsr24, "BSR24", MEP_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_jmp, "JMP", MEP_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_jmp24, "JMP24", MEP_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_jsr, "JSR", MEP_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ret, "RET", MEP_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_repeat, "REPEAT", MEP_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_erepeat, "EREPEAT", MEP_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_stc_lp, "STC_LP", MEP_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_stc_hi, "STC_HI", MEP_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_stc_lo, "STC_LO", MEP_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_stc, "STC", MEP_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ldc_lp, "LDC_LP", MEP_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ldc_hi, "LDC_HI", MEP_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ldc_lo, "LDC_LO", MEP_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ldc, "LDC", MEP_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE } },
> +  { mep_sem_di, "DI", MEP_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ei, "EI", MEP_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_reti, "RETI", MEP_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_halt, "HALT", MEP_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sleep, "SLEEP", MEP_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_swi, "SWI", MEP_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_break, "BREAK", MEP_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_syncm, "SYNCM", MEP_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_stcb, "STCB", MEP_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ldcb, "LDCB", MEP_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mep_sem_bsetm, "BSETM", MEP_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bclrm, "BCLRM", MEP_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bnotm, "BNOTM", MEP_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_btstm, "BTSTM", MEP_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_tas, "TAS", MEP_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_cache, "CACHE", MEP_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_mul, "MUL", MEP_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_mulu, "MULU", MEP_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_mulr, "MULR", MEP_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mep_sem_mulru, "MULRU", MEP_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mep_sem_madd, "MADD", MEP_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_maddu, "MADDU", MEP_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_maddr, "MADDR", MEP_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mep_sem_maddru, "MADDRU", MEP_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE } },
> +  { mep_sem_div, "DIV", MEP_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
> +  { mep_sem_divu, "DIVU", MEP_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE } },
> +  { mep_sem_dret, "DRET", MEP_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_dbreak, "DBREAK", MEP_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ldz, "LDZ", MEP_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_abs, "ABS", MEP_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ave, "AVE", MEP_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_min, "MIN", MEP_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_max, "MAX", MEP_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_minu, "MINU", MEP_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_maxu, "MAXU", MEP_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_clip, "CLIP", MEP_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_clipu, "CLIPU", MEP_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sadd, "SADD", MEP_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ssub, "SSUB", MEP_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_saddu, "SADDU", MEP_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ssubu, "SSUBU", MEP_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_swcp, "SWCP", MEP_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lwcp, "LWCP", MEP_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_smcp, "SMCP", MEP_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lmcp, "LMCP", MEP_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_swcpi, "SWCPI", MEP_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lwcpi, "LWCPI", MEP_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_smcpi, "SMCPI", MEP_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lmcpi, "LMCPI", MEP_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_swcp16, "SWCP16", MEP_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lwcp16, "LWCP16", MEP_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_smcp16, "SMCP16", MEP_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lmcp16, "LMCP16", MEP_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sbcpa, "SBCPA", MEP_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lbcpa, "LBCPA", MEP_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_shcpa, "SHCPA", MEP_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lhcpa, "LHCPA", MEP_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_swcpa, "SWCPA", MEP_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lwcpa, "LWCPA", MEP_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_smcpa, "SMCPA", MEP_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lmcpa, "LMCPA", MEP_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sbcpm0, "SBCPM0", MEP_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lbcpm0, "LBCPM0", MEP_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_shcpm0, "SHCPM0", MEP_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lhcpm0, "LHCPM0", MEP_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_swcpm0, "SWCPM0", MEP_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lwcpm0, "LWCPM0", MEP_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_smcpm0, "SMCPM0", MEP_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lmcpm0, "LMCPM0", MEP_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sbcpm1, "SBCPM1", MEP_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lbcpm1, "LBCPM1", MEP_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_shcpm1, "SHCPM1", MEP_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lhcpm1, "LHCPM1", MEP_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_swcpm1, "SWCPM1", MEP_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lwcpm1, "LWCPM1", MEP_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_smcpm1, "SMCPM1", MEP_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_lmcpm1, "LMCPM1", MEP_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bcpeq, "BCPEQ", MEP_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bcpne, "BCPNE", MEP_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bcpat, "BCPAT", MEP_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bcpaf, "BCPAF", MEP_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_synccp, "SYNCCP", MEP_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_jsrv, "JSRV", MEP_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_bsrv, "BSRV", MEP_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_sim_syscall, "SIM_SYSCALL", MEP_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_0, "RI_0", MEP_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_1, "RI_1", MEP_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_2, "RI_2", MEP_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_3, "RI_3", MEP_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_4, "RI_4", MEP_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_5, "RI_5", MEP_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_6, "RI_6", MEP_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_7, "RI_7", MEP_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_8, "RI_8", MEP_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_9, "RI_9", MEP_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_10, "RI_10", MEP_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_11, "RI_11", MEP_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_12, "RI_12", MEP_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_13, "RI_13", MEP_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_14, "RI_14", MEP_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_15, "RI_15", MEP_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_17, "RI_17", MEP_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_20, "RI_20", MEP_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_21, "RI_21", MEP_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_22, "RI_22", MEP_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_23, "RI_23", MEP_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_24, "RI_24", MEP_INSN_RI_24, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_25, "RI_25", MEP_INSN_RI_25, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_26, "RI_26", MEP_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_16, "RI_16", MEP_INSN_RI_16, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_18, "RI_18", MEP_INSN_RI_18, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
> +  { mep_sem_ri_19, "RI_19", MEP_INSN_RI_19, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE } },
>  
>  };
>  
> Index: sid/component/cgen-cpu/mep/mep-desc.h
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-desc.h,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep-desc.h
> --- sid/component/cgen-cpu/mep/mep-desc.h 5 Feb 2007 20:28:40 -0000 1.1
> +++ sid/component/cgen-cpu/mep/mep-desc.h 3 Feb 2009 01:53:51 -0000
> @@ -2,7 +2,7 @@
>  
>  THIS FILE IS MACHINE GENERATED WITH CGEN.
>  
> -Copyright (C) 2000-2005 Red Hat, Inc.
> +Copyright (C) 2000-2007 Red Hat, Inc.
>  
>  This file is part of the Red Hat simulators.
>  
> @@ -26,14 +26,6 @@ typedef enum major {
>   , MAJ_12, MAJ_13, MAJ_14, MAJ_15
>  } MAJOR;
>  
> -/* Enum declaration for condition opcode enum.  */
> -typedef enum fmax_cond {
> -  FMAX_F, FMAX_U, FMAX_E, FMAX_UE
> - , FMAX_L, FMAX_UL, FMAX_LE, FMAX_ULE
> - , FMAX_FI, FMAX_UI, FMAX_EI, FMAX_UEI
> - , FMAX_LI, FMAX_ULI, FMAX_LEI, FMAX_ULEI
> -} FMAX_COND;
> -
>  // Insn attribute indices.
>  
>  /* Enum declaration for cgen_insn attrs.  */
> @@ -62,8 +54,7 @@ typedef enum mach_attr {
>  
>  /* Enum declaration for instruction set selection.  */
>  typedef enum isa_attr {
> -  ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2, ISA_EXT_COP2_16
> - , ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64, ISA_MAX
> +  ISA_MEP, ISA_EXT_CORE1, ISA_MAX
>  } ISA_ATTR;
>  
>  /* Enum declaration for datatype to use for C intrinsics mapping.  */
> @@ -75,7 +66,7 @@ typedef enum cdata_attr {
>  
>  /* Enum declaration for .  */
>  typedef enum config_attr {
> -  CONFIG_NONE, CONFIG_SIMPLE, CONFIG_FMAX
> +  CONFIG_NONE, CONFIG_DEFAULT
>  } CONFIG_ATTR;
>  
>  // Insn attributes.
> Index: sid/component/cgen-cpu/mep/mep.h
> ===================================================================
> RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep.h,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/cgen-cpu/mep/mep.h
> --- sid/component/cgen-cpu/mep/mep.h 5 Feb 2007 20:28:40 -0000 1.1
> +++ sid/component/cgen-cpu/mep/mep.h 3 Feb 2009 01:53:51 -0000
> @@ -16,8 +16,6 @@ using namespace cgen;
>  using sidutil::callback_pin;
>  
>  // begin-fpu-includes
> -#include "fmax-fp.h"
> -using sidutil::fmax_fp;
>  // end-fpu-includes
>  
>  namespace mep
> @@ -27,7 +25,6 @@ namespace mep
>        // Include cgen generated elements.
>  #include "mep-cpu.h"
>  // begin-copro-cpu-includes
> -#include "fmax-cpu.h"
>  // end-copro-cpu-includes
>  
>      public:
> Index: sid/component/families/mep/ChangeLog
> ===================================================================
> RCS file: /cvs/src/src/sid/component/families/mep/ChangeLog,v
> retrieving revision 1.2
> diff -p -U3 -r1.2  sid/component/families/mep/ChangeLog
> --- sid/component/families/mep/ChangeLog 31 Oct 2007 14:48:04 -0000 1.2
> +++ sid/component/families/mep/ChangeLog 3 Feb 2009 01:53:51 -0000
> @@ -1,3 +1,7 @@
> +2009-02-02  DJ Delorie  <[hidden email]>
> +
> + * mm_int.h (no_relation_component): Update to new MeP configuration.
> +
>  2007-10-31  Dave Brolley  <[hidden email]>
>  
>          * components.cxx (mepfamily_component_library): Correct DLLEXPORT
> Index: sid/component/families/mep/mm_int.h
> ===================================================================
> RCS file: /cvs/src/src/sid/component/families/mep/mm_int.h,v
> retrieving revision 1.1
> diff -p -U3 -r1.1  sid/component/families/mep/mm_int.h
> --- sid/component/families/mep/mm_int.h 5 Feb 2007 20:28:40 -0000 1.1
> +++ sid/component/families/mep/mm_int.h 3 Feb 2009 01:53:51 -0000
> @@ -48,7 +48,7 @@ private:
>    friend class mm_int_interface;
>  
>    // parameters
> -  static const int max_modules = 2;
> +  static const int max_modules = 1;
>    static const int max_channels = 0x100 / 4;
>    // Control bus.
>    mm_int_interface ctrl_bus;
> Index: sid/main/dynamic/ChangeLog
> ===================================================================
> RCS file: /cvs/src/src/sid/main/dynamic/ChangeLog,v
> retrieving revision 1.45
> diff -p -U3 -r1.45  sid/main/dynamic/ChangeLog
> --- sid/main/dynamic/ChangeLog 17 Jun 2008 18:11:51 -0000 1.45
> +++ sid/main/dynamic/ChangeLog 3 Feb 2009 01:53:51 -0000
> @@ -1,3 +1,8 @@
> +2009-02-02  DJ Delorie  <[hidden email]>
> +
> + * mepCfg.cxx (MepMemCfg): Update to new MeP configuration.
> + * mainDynamic.cxx (mk_sample): Update to new MeP configuration.
> +
>  2008-06-17  Dave Brolley  <[hidden email]>
>  
>   * mainDynamic.cxx (usage): Document --reversible.
> Index: sid/main/dynamic/mainDynamic.cxx
> ===================================================================
> RCS file: /cvs/src/src/sid/main/dynamic/mainDynamic.cxx,v
> retrieving revision 1.12
> diff -p -U3 -r1.12  sid/main/dynamic/mainDynamic.cxx
> --- sid/main/dynamic/mainDynamic.cxx 17 Jun 2008 18:11:51 -0000 1.12
> +++ sid/main/dynamic/mainDynamic.cxx 3 Feb 2009 01:53:52 -0000
> @@ -48,50 +48,30 @@ mk_basic (const string name, SessionCfg
>  #ifdef SIDTARGET_MEP
>  /* begin-mepcfgtool-factories */
>  static BoardCfg *
> -mk_simple (const string name, SessionCfg *sess)
> +mk_default (const string name, SessionCfg *sess)
>  {
> -  MepBoardCfg *b = new MepBoardCfg (name, "simple", sess);
> -
> -  b->set_core_type (MEP_CORE_C2);
> +  MepBoardCfg *b = new MepBoardCfg (name, "default", sess);
> +  b->set_core_type (MEP_CORE_C4);
>    b->set_cpu ("mep-ext1");
>    b->add_irq_board ();
> -  b->set_core_id (1);
> -  b->set_intc_channel_bitw (8);
> -  b->set_intc_level (15);
> -  b->set_opt_biu (64);
> -  b->set_endian ("big");
> -  b->set_opt_abs (false);
> -  b->set_opt_ave (false);
> -  b->set_opt_bit (false);
> -  b->set_opt_clp (false);
> -  b->set_opt_div (false);
> -  b->set_opt_ldz (false);
> -  b->set_opt_min (false);
> -  b->set_opt_mul (false);
> -  b->set_opt_sat (false);
> -  b->set_opt_dsu (false);
> -  b->set_opt_uci (false);
> -  return b;
> -}
> -
> -static BoardCfg *
> -mk_fmax (const string name, SessionCfg *sess)
> -{
> -  MepBoardCfg *b = new MepBoardCfg (name, "fmax", sess);
> -
> -  b->set_core_type (MEP_CORE_C2);
> -  b->set_cpu ("mep-ext2");
> -  b->add_irq_board ();
> -  b->set_core_id (2);
> -  b->set_intc_channel_bitw (8);
> +  b->set_imem_size (32);
> +  b->set_dmem_bank_num (4);
> +  b->set_dmem_size (128);
> +  b->set_icache_size (16);
> +  b->set_icache_way (1);
> +  b->set_icache_line_size (32);
> +  b->set_dcache_size (16);
> +  b->set_dcache_way (1);
> +  b->set_dcache_line_size (32);
> +  b->set_core_id (50);
> +  b->set_intc_channel_bitw (32);
>    b->set_intc_level (15);
> -  b->add_cop ("fmax_cop", 0);
> -  b->set_cop_data_bus_width (32);
> -  b->set_cop_ccr ( 0, 0x00000101);
> -  b->set_cop_ccr ( 1, 0x00000000);
> -  b->set_cop_ccr (15, 0x00000000);
> +  b->set_icache_cwf (false);
> +  b->set_dcache_cwf (false);
> +  b->add_timer (4);
> +  b->add_dmac (6, 64, true);
>    b->set_opt_biu (64);
> -  b->set_endian ("big");
> +  b->set_endian ("little");
>    b->set_opt_abs (true);
>    b->set_opt_ave (true);
>    b->set_opt_bit (true);
> @@ -113,8 +93,7 @@ static boardspec boards [] = {
>    {"basic", "basic cpu + memory board", & mk_basic},
>  #ifdef SIDTARGET_MEP
>  /* begin-mepcfgtool-boards */
> -  { "simple", "MeP custom board 'simple'", & mk_simple },
> -  { "fmax", "MeP custom board 'fmax'", & mk_fmax },
> +  { "default", "MeP custom board 'default'", & mk_default },
>  /* end-mepcfgtool-boards */
>  #endif /* SIDTARGET_MEP */
>  #if defined (SIDTARGET_SH) || defined (SIDTARGET_SH64)
> Index: sid/main/dynamic/mepCfg.cxx
> ===================================================================
> RCS file: /cvs/src/src/sid/main/dynamic/mepCfg.cxx,v
> retrieving revision 1.3
> diff -p -U3 -r1.3  sid/main/dynamic/mepCfg.cxx
> --- sid/main/dynamic/mepCfg.cxx 6 Nov 2007 21:06:05 -0000 1.3
> +++ sid/main/dynamic/mepCfg.cxx 3 Feb 2009 01:53:52 -0000
> @@ -263,7 +263,7 @@ public:
>      // begin-global-memory-regions
>      mems.push_back (new MepMemRegionCfg ("shared-mem0", 0x0, 0x200000, 10, 1, false, true));
>      mems.push_back (new MepMemRegionCfg ("shared-mem1", 0x800000, 0x800000, 10, 1, true, false));
> -    mems.push_back (new MepMemRegionCfg ("shared-mem2", 0x80800000, 0x800000, 10, 1, false, false));
> +    mems.push_back (new MepMemRegionCfg ("shared-mem2", 0x80000000, 0x800000, 10, 1, true, false));
>      // end-global-memory-regions
>  
>      // begin-shadow-regions
> @@ -1871,6 +1871,9 @@ void MepBoardCfg::configure_icache ()
>  
>    // Pass the appropriate peripheral regions
>    // begin-icache-settings
> +  if (get_module_type () == "default")
> +    {
> +    }
>    // end-icache-settings
>  
>    // pass the imem/dmem space, which is always present.
> @@ -1949,6 +1952,9 @@ void MepBoardCfg::configure_dcache ()
>  
>    // Pass the appropriate peripheral regions
>    // begin-dcache-settings
> +  if (get_module_type () == "default")
> +    {
> +    }
>    // end-dcache-settings
>  
>    // pass the imem/dmem space, which is always present.
>  

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Re: [mep] configuration regen

DJ Delorie-2

Strictly a regen, no hand-waving.
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Re: [mep] configuration regen

Dave Brolley-2
OK. Go ahead and commit then.

DJ Delorie wrote:
> Strictly a regen, no hand-waving.
>  

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Re: [mep] configuration regen

DJ Delorie-2

> OK. Go ahead and commit then.

Thanks, committed.