Hi, I'm a graduate student in a university in South Korea and my
current asignment is to compare SID with other simulators such as
Virtio, SimOS, ProEmulator, etc. Even though i have some experience
with SID (had struggled to compile it on CygWin and had made simple
components in C and Tcl), i have no experience with those other
simulators. Honestly, i am quite new with this kind of world. My major
is computer science and i have never touched any real boards or
simulators before i met SID. In fact, it took me a while to understand
what the so called board is (dictionary didnt help).
I need to know what are the advantages and disadvantages of SID, what
is its unique features, how well does it performs and so on. I have
tried to search but there are very few documents/articles about SID
and not to mention that the name SID "googled" to many different kind
of unrelated stuffs which renders my searchs really ineffective.
So, i was wondering if i could get some comments, insights, clues,
references, google search keywords or anything from the experts of
this forum. Thanks in advance.
On Fri, Feb 02, 2007 at 02:11:46PM +0900, hadipurnawan satria wrote:
> Hi, I'm a graduate student in a university in South Korea and my
> current asignment is to compare SID with other simulators such as
> Virtio, SimOS, ProEmulator, etc. [...]
> [...] In fact, it took me a while to understand what the so called
> board is (dictionary didnt help).
Sorry about that! "circuit board" would have been too long.
> I need to know what are the advantages and disadvantages of SID,
> what is its unique features, how well does it performs and so
> on. [...]
It might be summarized like this. We aimed to build something small
and simple, using a small fixed API, enabling straightforward
composition of part models (and their optional GUIs) based on a
hardware assembly metaphor. It is suitable for consideration as an
integration platform for other simulators (interconnecting models from
different simulators, as has been done with BOCHS, and also with a
live Verilog system). Its "plugin" mechanism allows separate
compilation and packaging of simulation components. Most of its
library of models have *not* been particularly tuned for performance,
and the architecture generally considers this an internal matter for
each component model.
As far as project dynamics goes, its improvements in recent years have
been customer-funded, and most or all of them are being released into
the GPL free software pool.
Do you need elaboration on any of these or other points?