[RFC] New opcodes port: Morpho ms1

classic Classic list List threaded Threaded
4 messages Options
Reply | Threaded
Open this post in threaded view
|

[RFC] New opcodes port: Morpho ms1

Dave Brolley
Hello,

On behalf of Red Hat I would like to commit the opcodes port for the
Morpho ms1. Attached is the patch minus the CGEN-generated sources which
I can make available should anyone wish to see them first.

Dave

? opcodes/ms1-asm.c
? opcodes/ms1-desc.c
? opcodes/ms1-desc.h
? opcodes/ms1-dis.c
? opcodes/ms1-ibld.c
? opcodes/ms1-opc.c
? opcodes/ms1-opc.h
Index: opcodes/Makefile.am
===================================================================
RCS file: /cvs/src/src/opcodes/Makefile.am,v
retrieving revision 1.83
diff -c -p -r1.83 Makefile.am
*** opcodes/Makefile.am 8 Jun 2005 17:27:40 -0000 1.83
--- opcodes/Makefile.am 8 Jun 2005 19:45:40 -0000
*************** HFILES = \
*** 34,39 ****
--- 34,40 ----
  iq2000-desc.h iq2000-opc.h \
  m32r-desc.h m32r-opc.h \
  mcore-opc.h \
+ ms1-desc.h ms1-opc.h \
  openrisc-desc.h openrisc-opc.h \
  sh-opc.h \
  sh64-opc.h \
*************** CFILES = \
*** 127,132 ****
--- 128,138 ----
  m10300-opc.c \
  mmix-dis.c \
  mmix-opc.c \
+ ms1-asm.c \
+ ms1-desc.c \
+ ms1-dis.c \
+ ms1-ibld.c \
+ ms1-opc.c \
  ns32k-dis.c \
  openrisc-asm.c \
  openrisc-desc.c \
*************** ALL_MACHINES = \
*** 241,246 ****
--- 247,257 ----
  mips16-opc.lo \
  mmix-dis.lo \
  mmix-opc.lo \
+ ms1-asm.lo \
+ ms1-desc.lo \
+ ms1-dis.lo \
+ ms1-ibld.lo \
+ ms1-opc.lo \
  msp430-dis.lo \
  ns32k-dis.lo \
  openrisc-asm.lo \
*************** uninstall_libopcodes:
*** 351,357 ****
 
  CLEANFILES = \
  stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \
! stamp-iq2000 stamp-xstormy16 \
  libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
 
 
--- 362,368 ----
 
  CLEANFILES = \
  stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \
! stamp-iq2000 stamp-ms1 stamp-xstormy16 \
  libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
 
 
*************** CGENDEPS = \
*** 367,379 ****
  $(CGENDIR)/opc-opinst.scm \
  cgen-asm.in cgen-dis.in cgen-ibld.in
 
! CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16
 
  if CGEN_MAINT
  IP2K_DEPS = stamp-ip2k
  M32R_DEPS = stamp-m32r
  FR30_DEPS = stamp-fr30
  FRV_DEPS = stamp-frv
  OPENRISC_DEPS = stamp-openrisc
  IQ2000_DEPS = stamp-iq2000
  XSTORMY16_DEPS = stamp-xstormy16
--- 378,391 ----
  $(CGENDIR)/opc-opinst.scm \
  cgen-asm.in cgen-dis.in cgen-ibld.in
 
! CGEN_CPUS = fr30 frv ip2k m32r ms1 openrisc xstormy16
 
  if CGEN_MAINT
  IP2K_DEPS = stamp-ip2k
  M32R_DEPS = stamp-m32r
  FR30_DEPS = stamp-fr30
  FRV_DEPS = stamp-frv
+ MS1_DEPS = stamp-ms1
  OPENRISC_DEPS = stamp-openrisc
  IQ2000_DEPS = stamp-iq2000
  XSTORMY16_DEPS = stamp-xstormy16
*************** IP2K_DEPS =
*** 382,387 ****
--- 394,400 ----
  M32R_DEPS =
  FR30_DEPS =
  FRV_DEPS =
+ MS1_DEPS =
  OPENRISC_DEPS =
  IQ2000_DEPS =
  XSTORMY16_DEPS =
*************** stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.c
*** 423,434 ****
 
  $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS)
  @true
- # .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so
- # copy those file to the regular place.
  stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc
  $(MAKE) run-cgen arch=frv prefix=frv options= \
  archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
 
  $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
  @true
  stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
--- 436,451 ----
 
  $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS)
  @true
  stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc
  $(MAKE) run-cgen arch=frv prefix=frv options= \
  archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
 
+ $(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MS1_DEPS)
+ @true
+ stamp-ms1: $(CGENDEPS) $(CPUDIR)/ms1.cpu $(CPUDIR)/ms1.opc
+ $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \
+ archfile=$(CPUDIR)/ms1.cpu opcfile=$(CPUDIR)/ms1.opc extrafiles=
+
  $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
  @true
  stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
*************** mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode
*** 746,751 ****
--- 763,787 ----
    $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
    opintl.h
  mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h
+ ms1-asm.lo: ms1-asm.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \
+   $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/xregex.h \
+   $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+ ms1-desc.lo: ms1-desc.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \
+   $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/libiberty.h \
+   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+ ms1-dis.lo: ms1-dis.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
+   $(INCDIR)/libiberty.h ms1-desc.h $(INCDIR)/opcode/cgen.h \
+   ms1-opc.h opintl.h
+ ms1-ibld.lo: ms1-ibld.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
+   ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h \
+   opintl.h $(INCDIR)/safe-ctype.h
+ ms1-opc.lo: ms1-opc.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \
+   $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h
  ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
    $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \
    $(INCDIR)/opcode/ns32k.h opintl.h
Index: opcodes/Makefile.in
===================================================================
RCS file: /cvs/src/src/opcodes/Makefile.in,v
retrieving revision 1.94
diff -c -p -r1.94 Makefile.in
*** opcodes/Makefile.in 8 Jun 2005 17:27:40 -0000 1.94
--- opcodes/Makefile.in 8 Jun 2005 19:45:40 -0000
*************** HFILES = \
*** 255,260 ****
--- 255,261 ----
  iq2000-desc.h iq2000-opc.h \
  m32r-desc.h m32r-opc.h \
  mcore-opc.h \
+ ms1-desc.h ms1-opc.h \
  openrisc-desc.h openrisc-opc.h \
  sh-opc.h \
  sh64-opc.h \
*************** CFILES = \
*** 349,354 ****
--- 350,360 ----
  m10300-opc.c \
  mmix-dis.c \
  mmix-opc.c \
+ ms1-asm.c \
+ ms1-desc.c \
+ ms1-dis.c \
+ ms1-ibld.c \
+ ms1-opc.c \
  ns32k-dis.c \
  openrisc-asm.c \
  openrisc-desc.c \
*************** ALL_MACHINES = \
*** 463,468 ****
--- 469,479 ----
  mips16-opc.lo \
  mmix-dis.lo \
  mmix-opc.lo \
+ ms1-asm.lo \
+ ms1-desc.lo \
+ ms1-dis.lo \
+ ms1-ibld.lo \
+ ms1-opc.lo \
  msp430-dis.lo \
  ns32k-dis.lo \
  openrisc-asm.lo \
*************** noinst_LIBRARIES = libopcodes.a
*** 527,533 ****
  POTFILES = $(HFILES) $(CFILES)
  CLEANFILES = \
  stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \
! stamp-iq2000 stamp-xstormy16 \
  libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
 
  CGENDIR = @cgendir@
--- 538,544 ----
  POTFILES = $(HFILES) $(CFILES)
  CLEANFILES = \
  stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \
! stamp-iq2000 stamp-ms1 stamp-xstormy16 \
  libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
 
  CGENDIR = @cgendir@
*************** CGENDEPS = \
*** 541,547 ****
  $(CGENDIR)/opc-opinst.scm \
  cgen-asm.in cgen-dis.in cgen-ibld.in
 
! CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16
  @CGEN_MAINT_FALSE@IP2K_DEPS =
  @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k
  @CGEN_MAINT_FALSE@M32R_DEPS =
--- 552,558 ----
  $(CGENDIR)/opc-opinst.scm \
  cgen-asm.in cgen-dis.in cgen-ibld.in
 
! CGEN_CPUS = fr30 frv ip2k m32r ms1 openrisc xstormy16
  @CGEN_MAINT_FALSE@IP2K_DEPS =
  @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k
  @CGEN_MAINT_FALSE@M32R_DEPS =
*************** CGEN_CPUS = fr30 frv ip2k m32r openrisc
*** 550,555 ****
--- 561,568 ----
  @CGEN_MAINT_TRUE@FR30_DEPS = stamp-fr30
  @CGEN_MAINT_FALSE@FRV_DEPS =
  @CGEN_MAINT_TRUE@FRV_DEPS = stamp-frv
+ @CGEN_MAINT_FALSE@MS1_DEPS =
+ @CGEN_MAINT_TRUE@MS1_DEPS = stamp-ms1
  @CGEN_MAINT_FALSE@OPENRISC_DEPS =
  @CGEN_MAINT_TRUE@OPENRISC_DEPS = stamp-openrisc
  @CGEN_MAINT_FALSE@IQ2000_DEPS =
*************** stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.c
*** 953,964 ****
 
  $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS)
  @true
- # .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so
- # copy those file to the regular place.
  stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc
  $(MAKE) run-cgen arch=frv prefix=frv options= \
  archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
 
  $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
  @true
  stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
--- 966,981 ----
 
  $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS)
  @true
  stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc
  $(MAKE) run-cgen arch=frv prefix=frv options= \
  archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles=
 
+ $(srcdir)/ms1-desc.h $(srcdir)/ms1-desc.c $(srcdir)/ms1-opc.h $(srcdir)/ms1-opc.c $(srcdir)/ms1-ibld.c $(srcdir)/ms1-asm.c $(srcdir)/ms1-dis.c: $(MS1_DEPS)
+ @true
+ stamp-ms1: $(CGENDEPS) $(srcdir)/../cpu/ms1.cpu $(srcdir)/../cpu/ms1.opc
+ $(MAKE) run-cgen arch=ms1 prefix=ms1 options= \
+ archfile=$(srcdir)/../cpu/ms1.cpu opcfile=$(srcdir)/../cpu/ms1.opc extrafiles=
+
  $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS)
  @true
  stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc
*************** mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode
*** 1276,1281 ****
--- 1293,1317 ----
    $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
    opintl.h
  mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h
+ ms1-asm.lo: ms1-asm.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \
+   $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/xregex.h \
+   $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+ ms1-desc.lo: ms1-desc.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \
+   $(INCDIR)/opcode/cgen.h ms1-opc.h opintl.h $(INCDIR)/libiberty.h \
+   $(INCDIR)/xregex.h $(INCDIR)/xregex2.h
+ ms1-dis.lo: ms1-dis.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
+   $(INCDIR)/libiberty.h ms1-desc.h $(INCDIR)/opcode/cgen.h \
+   ms1-opc.h opintl.h
+ ms1-ibld.lo: ms1-ibld.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \
+   ms1-desc.h $(INCDIR)/opcode/cgen.h ms1-opc.h \
+   opintl.h $(INCDIR)/safe-ctype.h
+ ms1-opc.lo: ms1-opc.c sysdep.h config.h \
+   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h ms1-desc.h \
+   $(INCDIR)/opcode/cgen.h ms1-opc.h $(INCDIR)/libiberty.h
  ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \
    $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \
    $(INCDIR)/opcode/ns32k.h opintl.h
Index: opcodes/configure
===================================================================
RCS file: /cvs/src/src/opcodes/configure,v
retrieving revision 1.75
diff -c -p -r1.75 configure
*** opcodes/configure 5 May 2005 09:17:31 -0000 1.75
--- opcodes/configure 8 Jun 2005 19:45:41 -0000
*************** if test x${all_targets} = xfalse ; then
*** 8727,8732 ****
--- 8727,8733 ----
  bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
  bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
  bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
+ bfd_ms1_arch) ta="$ta ms1-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;;
  bfd_msp430_arch) ta="$ta msp430-dis.lo" ;;
  bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;;
  bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;;
Index: opcodes/configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.57
diff -c -p -r1.57 configure.in
*** opcodes/configure.in 5 May 2005 09:17:34 -0000 1.57
--- opcodes/configure.in 8 Jun 2005 19:45:41 -0000
*************** if test x${all_targets} = xfalse ; then
*** 187,192 ****
--- 187,193 ----
  bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;;
  bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;;
  bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;;
+ bfd_ms1_arch) ta="$ta ms1-asm.lo ms1-desc.lo ms1-dis.lo ms1-ibld.lo ms1-opc.lo" using_cgen=yes ;;
  bfd_msp430_arch) ta="$ta msp430-dis.lo" ;;
  bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;;
  bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;;
Index: opcodes/disassemble.c
===================================================================
RCS file: /cvs/src/src/opcodes/disassemble.c,v
retrieving revision 1.51
diff -c -p -r1.51 disassemble.c
*** opcodes/disassemble.c 7 May 2005 07:34:27 -0000 1.51
--- opcodes/disassemble.c 8 Jun 2005 19:45:41 -0000
***************
*** 51,56 ****
--- 51,57 ----
  #define ARCH_mmix
  #define ARCH_mn10200
  #define ARCH_mn10300
+ #define ARCH_ms1
  #define ARCH_msp430
  #define ARCH_ns32k
  #define ARCH_openrisc
*************** disassembler (abfd)
*** 233,238 ****
--- 234,244 ----
        disassemble = print_insn_maxq_little;
        break;
  #endif
+ #ifdef ARCH_ms1
+     case bfd_arch_ms1:
+       disassemble = print_insn_ms1;
+       break;
+ #endif
  #ifdef ARCH_msp430
      case bfd_arch_msp430:
        disassemble = print_insn_msp430;
Reply | Threaded
Open this post in threaded view
|

Re: [RFC] New opcodes port: Morpho ms1

Aldy Hernandez-2
Ping.

Could someone review and/or take a look at this?  It doesn't affect
anything else, and I have more patches pending on this one (as well as
GCC and newlib code).

Thanks.
Aldy

 > Hello,
 > On behalf of Red Hat I would like to commit the opcodes port for the
 > Morpho ms1. Attached is the patch minus the CGEN-generated sources
 > which I can make available should anyone wish to see them first.
Reply | Threaded
Open this post in threaded view
|

Re: [RFC] New opcodes port: Morpho ms1

Nick Clifton
In reply to this post by Dave Brolley
Hi Dave,

> On behalf of Red Hat I would like to commit the opcodes port for the
> Morpho ms1. Attached is the patch minus the CGEN-generated sources which
> I can make available should anyone wish to see them first.

This patch is approved provided that:

   a).  You create a set of suitable ChangeLog entries to accompany the
changes.  (Really these should have been included with the patch
submission).

   b).  You have checked in the cgen/cpu/ms1.* files.

   c).  You then generate the opcodes/ms1* files and check these in as well.

ie please only check in this patch when it will not prevent a toolchain
configured with --enable-targets=all from configuring and building
properly.  In fact please check that this works before you commit your
patch.

Cheers
   Nick
Reply | Threaded
Open this post in threaded view
|

Re: [RFC] New opcodes port: Morpho ms1

Dave Brolley-2
Nick Clifton wrote:

> This patch is approved provided that:
>
>   a).  You create a set of suitable ChangeLog entries to accompany the
> changes.  (Really these should have been included with the patch
> submission).

You're right. Sorry for the omission. Done. See below.

>
>   b).  You have checked in the cgen/cpu/ms1.* files.

Done. Copyright has been assigned to the FSF and the files have been
committed to the cpu directory.

>   c).  You then generate the opcodes/ms1* files and check these in as
> well.

Done

>
> ie please only check in this patch when it will not prevent a
> toolchain configured with --enable-targets=all from configuring and
> building properly.  In fact please check that this works before you
> commit your patch.

Done. The patch has been committed.

Thanks!
Dave