[Patch] MIPS opcode table: Add ISA masks for mips32r2 instructions

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[Patch] MIPS opcode table: Add ISA masks for mips32r2 instructions

David Ung

This patch adds the I33 (MIPS32r2) mask to instructions that belongs to
that ISA class in the MIPS opcode table.
regressions ok.

David.

        * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
        ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
        floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
        nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
        rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

Index: binutils/src/opcodes/mips-opc.c
===================================================================
--- binutils.orig/src/opcodes/mips-opc.c 2006-01-26 11:26:13.000000000 +0000
+++ binutils/src/opcodes/mips-opc.c 2006-01-26 12:11:44.000000000 +0000
@@ -169,7 +169,7 @@
    instruction name anyhow.  */
 /* name,    args, match,    mask, pinfo,           pinfo2, membership */
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           0, I4|I32|G3 },
-{"prefx",   "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4 },
+{"prefx",   "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
 {"nop",     "",         0x00000000, 0xffffffff, 0,               INSN2_ALIAS, I1      }, /* sll */
 {"ssnop",   "",         0x00000040, 0xffffffff, 0,               INSN2_ALIAS, I32|N55 }, /* sll */
 {"ehb",     "",         0x000000c0, 0xffffffff, 0,               INSN2_ALIAS, I33 }, /* sll */
@@ -460,8 +460,8 @@
 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
 {"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,           0, I3|I32|T3},
-{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
-{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
+{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
+{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, 0, I3|I33 },
 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
 {"cfc0",    "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
@@ -482,12 +482,12 @@
 {"cttc1",   "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
 {"cttc1",   "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
 {"cttc2",   "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
-{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
+{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, 0, I1 },
 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
-{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
-{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
-{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
+{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
+{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, 0, I3|I33 },
+{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, 0, I3|I33 },
 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5 },
@@ -638,8 +638,8 @@
 {"evpe",    "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
 {"evpe",    "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,     0, I33 },
-{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
-{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
+{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
+{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, 0, I3|I33 },
 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
 {"flushi",  "", 0xbc010000, 0xffffffff, 0, 0, L1 },
@@ -695,7 +695,7 @@
 {"ldl",    "t,A(b)", 0,    (int) M_LDL_AB, INSN_MACRO, 0, I3 },
 {"ldr",    "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
 {"ldr",     "t,A(b)", 0,    (int) M_LDR_AB, INSN_MACRO, 0, I3 },
-{"ldxc1",   "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I4 },
+{"ldxc1",   "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I4|I33 },
 {"lh",      "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
 {"lh",      "t,A(b)", 0,    (int) M_LH_AB, INSN_MACRO, 0, I1 },
 {"lhu",     "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
@@ -736,7 +736,7 @@
 {"fork",    "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
 {"lwu",     "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
 {"lwu",     "t,A(b)", 0,    (int) M_LWU_AB, INSN_MACRO, 0, I3 },
-{"lwxc1",   "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I4 },
+{"lwxc1",   "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, 0, I4|I33 },
 {"macc",    "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412    },
 {"macc",    "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5      },
 {"maccs",   "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412    },
@@ -751,8 +751,8 @@
 {"maccus",  "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412    },
 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0, P3      },
 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0, P3      },
-{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0, I4 },
-{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0, I4 },
+{"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0, I4|I33 },
+{"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0, I4|I33 },
 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0, I5 },
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0, L1 },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0, I32|N55},
@@ -844,8 +844,8 @@
 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
 /* move is at the top of the table.  */
 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
-{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4 },
-{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 },
+{"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
+{"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 },
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1     },
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0, I32|N55 },
@@ -940,11 +940,11 @@
 {"neg.d",   "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
 {"neg.s",   "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
 {"neg.ps",  "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5 },
-{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4 },
-{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 },
+{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
+{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 },
-{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4 },
-{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4 },
+{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
+{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5 },
 /* nop is at the start of the table.  */
 {"nor",     "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
@@ -990,9 +990,9 @@
 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 },
 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
-{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4 },
+{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
-{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4 },
+{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
 {"recip1.d",  "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
 {"recip1.s",  "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
@@ -1025,13 +1025,13 @@
 {"rotr",    "d,v,t", 0,    (int) M_ROR, INSN_MACRO, 0, I33 },
 {"rotr",    "d,v,I", 0,    (int) M_ROR_I, INSN_MACRO, 0, I33 },
 {"rotrv",   "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33 },
-{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
+{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
-{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4 },
+{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
-{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4 },
+{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
 {"rsqrt1.d",  "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
 {"rsqrt1.s",  "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
@@ -1071,7 +1071,7 @@
 {"sdl",     "t,A(b)", 0,    (int) M_SDL_AB, INSN_MACRO, 0, I3 },
 {"sdr",     "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
 {"sdr",     "t,A(b)", 0,    (int) M_SDR_AB, INSN_MACRO, 0, I3 },
-{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I4 },
+{"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I4|I33 },
 {"seb",     "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
 {"seh",     "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
 {"selsl",   "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
@@ -1177,7 +1177,7 @@
 {"swr",     "t,A(b)", 0,    (int) M_SWR_AB, INSN_MACRO, 0, I1 },
 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
-{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I4 },
+{"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I4|I33 },
 {"sync",    "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
 {"sync.p",  "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
 {"sync.l",  "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
@@ -1218,8 +1218,8 @@
 {"tne",     "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
 {"tne",     "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */
 {"tne",     "s,I", 0,    (int) M_TNE_I, INSN_MACRO, 0, I2 },
-{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3 },
-{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, 0, I3 },
+{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
+{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, 0, I3|I33 },
 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
 {"trunc.w.d", "D,S,t", 0,    (int) M_TRUNCWD, INSN_MACRO, 0, I1 },


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Re: [Patch] MIPS opcode table: Add ISA masks for mips32r2 instructions

Thiemo Seufer
On Thu, Jan 26, 2006 at 01:05:01PM +0000, David Ung wrote:

>
> This patch adds the I33 (MIPS32r2) mask to instructions that belongs to
> that ISA class in the MIPS opcode table.
> regressions ok.
>
> David.
>
> * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
> ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
> floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
> nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
> rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.

Ok (with proper ChangeLog format).


Thiemo