PPC add MUTEX_HINTS atomic ops for POWER6

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PPC add MUTEX_HINTS atomic ops for POWER6

Steven Munroe
POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
The Mutex Hint is added as an optional 4th operand to lwarx/ldarx
instructions.  This is a hint to the hardware to expect additional
updates adjacent to the lock word or not.   If we are acquiring a Mutex,
the hint should be true.  Otherwise we releasing a Mutex or doing a
simple atomic operation.  In that case we don't expect addtional updates
adjacent to the lock word after the Store Conditional and the hint
should be false.

The attached patches defines MUTEX_HINT_ACQ and MUTEX_HINT_REL macros
and uses them as in the appropriate atomic *_acq and *_rel macros to
(conditionally) add the 4th (hint) operand to lwarx. Simple atomic
operations (add, increment, decrement) should use the default
(equivalent to MUTEX_HINT_REL) 3 operand lwarx/ldarx instuctions.



2007-03-19  Steven Munroe  <[hidden email]>

        * sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
        (__lll_robust_trylock): Add MUTEX_HINT_ACQ to lwarx instruction.

diff -urN libc25-cvstip-20070126/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h libc25/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h
--- libc25-cvstip-20070126/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h 2006-07-29 00:06:07.000000000 -0500
+++ libc25/nptl/sysdeps/unix/sysv/linux/powerpc/lowlevellock.h 2007-03-19 16:42:46.976248752 -0500
@@ -1,4 +1,4 @@
-/* Copyright (C) 2003, 2004, 2006 Free Software Foundation, Inc.
+/* Copyright (C) 2003, 2004, 2006, 2007 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
    Contributed by Paul Mackerras <[hidden email]>, 2003.
 
@@ -25,7 +25,6 @@
 #include <bits/pthreadtypes.h>
 #include <atomic.h>
 
-
 #ifndef __NR_futex
 # define __NR_futex 221
 #endif
@@ -133,7 +132,7 @@
 /* Set *futex to ID if it is 0, atomically.  Returns the old value */
 #define __lll_robust_trylock(futex, id) \
   ({ int __val;      \
-     __asm __volatile ("1: lwarx %0,0,%2\n"      \
+     __asm __volatile ("1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n"      \
        " cmpwi 0,%0,0\n"      \
        " bne 2f\n"      \
        " stwcx. %3,0,%2\n"      \

2007-03-19  Steven Munroe  <[hidden email]>

        * sysdeps/powerpc/bits/atomic.h
        [!MUTEX_HINT_ACQ]: Define MUTEX_HINT_ACQ.
        [!MUTEX_HINT_REL]: Define MUTEX_HINT_REL.
        (__arch_compare_and_exchange_val_32_acq): Add MUTEX_HINT_ACQ to lwarx.
        (__arch_compare_and_exchange_val_32_rel): Add MUTEX_HINT_REL to lwarx.
        (__arch_atomic_exchange_val_32_acq): Add MUTEX_HINT_ACQ to lwarx.
        (__arch_atomic_exchange_rel_32_rel): Add MUTEX_HINT_REL to lwarx.
        * sysdeps/powerpc/powerpc32/bits/atomic.h [_ARCH_PWR6 || _ARCH_PWR6X]:
        Define MUTEX_HINT_ACQ as ",1" and MUTEX_HINT_REL as ",0".
        (__arch_compare_and_exchange_bool_32_acq): Add MUTEX_HINT_ACQ to lwarx.
        (__arch_compare_and_exchange_bool_32_rel): Add MUTEX_HINT_REL to lwarx.
        * sysdeps/powerpc/powerpc64/bits/atomic.h [_ARCH_PWR6 || _ARCH_PWR6D]:
        Define MUTEX_HINT_ACQ as ",1" and MUTEX_HINT_REL as ",0".
        (__arch_compare_and_exchange_bool_32_acq): Add MUTEX_HINT_ACQ to lwarx.
        (__arch_compare_and_exchange_bool_32_rel): Add MUTEX_HINT_REL to lwarx.
        (__arch_compare_and_exchange_bool_64_acq): Add MUTEX_HINT_ACQ to lwarx.
        (__arch_compare_and_exchange_bool_64_rel): Add MUTEX_HINT_REL to lwarx.
        (__arch_compare_and_exchange_val_64_acq): Add MUTEX_HINT_ACQ to lwarx.
        (__arch_compare_and_exchange_val_64_rel): Add MUTEX_HINT_REL to lwarx.
        (__arch_atomic_exchange_val_64_acq): Add MUTEX_HINT_ACQ to lwarx.
        (__arch_atomic_exchange_rel_64_rel): Add MUTEX_HINT_REL to lwarx.

diff -urN libc25-cvstip-20070126/sysdeps/powerpc/bits/atomic.h libc25/sysdeps/powerpc/bits/atomic.h
--- libc25-cvstip-20070126/sysdeps/powerpc/bits/atomic.h 2004-09-08 01:08:11.000000000 -0500
+++ libc25/sysdeps/powerpc/bits/atomic.h 2007-02-20 14:36:14.000000000 -0600
@@ -70,6 +70,13 @@
 # endif
 #endif
 
+#ifndef MUTEX_HINT_ACQ
+# define MUTEX_HINT_ACQ
+#endif
+#ifndef MUTEX_HINT_REL
+# define MUTEX_HINT_REL
+#endif
+
 #define atomic_full_barrier() __asm ("sync" ::: "memory")
 #define atomic_write_barrier() __asm ("eieio" ::: "memory")
 
@@ -78,7 +85,7 @@
       __typeof (*(mem)) __tmp;      \
       __typeof (mem)  __memp = (mem);      \
       __asm __volatile (      \
-        "1: lwarx %0,0,%1\n"      \
+        "1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n"      \
         " cmpw %0,%2\n"      \
         " bne 2f\n"      \
         " stwcx. %3,0,%1\n"      \
@@ -95,7 +102,7 @@
       __typeof (*(mem)) __tmp;      \
       __typeof (mem)  __memp = (mem);      \
       __asm __volatile (__ARCH_REL_INSTR "\n"      \
-        "1: lwarx %0,0,%1\n"      \
+        "1: lwarx %0,0,%1" MUTEX_HINT_REL "\n"      \
         " cmpw %0,%2\n"      \
         " bne 2f\n"      \
         " stwcx. %3,0,%1\n"      \
@@ -111,7 +118,7 @@
   ({      \
     __typeof (*mem) __val;      \
     __asm __volatile (      \
-      "1: lwarx %0,0,%2\n"      \
+      "1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n"      \
       " stwcx. %3,0,%2\n"      \
       " bne- 1b\n"      \
       "   " __ARCH_ACQ_INSTR      \
@@ -125,7 +132,7 @@
   ({      \
     __typeof (*mem) __val;      \
     __asm __volatile (__ARCH_REL_INSTR "\n"      \
-      "1: lwarx %0,0,%2\n"      \
+      "1: lwarx %0,0,%2" MUTEX_HINT_REL "\n"      \
       " stwcx. %3,0,%2\n"      \
       " bne- 1b"      \
       : "=&r" (__val), "=m" (*mem)      \
diff -urN libc25-cvstip-20070126/sysdeps/powerpc/powerpc32/bits/atomic.h libc25/sysdeps/powerpc/powerpc32/bits/atomic.h
--- libc25-cvstip-20070126/sysdeps/powerpc/powerpc32/bits/atomic.h 2006-04-04 03:18:49.000000000 -0500
+++ libc25/sysdeps/powerpc/powerpc32/bits/atomic.h 2007-03-19 16:01:25.267246624 -0500
@@ -1,5 +1,5 @@
 /* Atomic operations.  PowerPC32 version.
-   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
    Contributed by Paul Mackerras <[hidden email]>, 2003.
 
@@ -18,6 +18,22 @@
    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
    02111-1307 USA.  */
 
+/*  POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
+    This is a hint to the hardware to expect additional updates adjacent
+    to the lock word or not.  If we are acquiring a Mutex, the hint
+    should be true. Otherwise we releasing a Mutex or doing a simple
+    atomic operation.  In that case we don't expect addtional updates
+    adjacent to the lock word after the Store Conditional and the hint
+    should be false.  */
+    
+#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
+#define MUTEX_HINT_ACQ ",1"
+#define MUTEX_HINT_REL ",0"
+#else
+#define MUTEX_HINT_ACQ
+#define MUTEX_HINT_REL
+#endif
+
 /*
  * The 32-bit exchange_bool is different on powerpc64 because the subf
  * does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
@@ -28,7 +44,7 @@
 ({      \
   unsigned int __tmp;      \
   __asm __volatile (      \
-    "1: lwarx %0,0,%1\n"      \
+    "1: lwarx %0,0,%1" MUTEX_HINT_ACQ "\n"      \
     " subf. %0,%2,%0\n"      \
     " bne 2f\n"      \
     " stwcx. %3,0,%1\n"      \
@@ -44,7 +60,7 @@
 ({      \
   unsigned int __tmp;      \
   __asm __volatile (__ARCH_REL_INSTR "\n"      \
-    "1: lwarx %0,0,%1\n"      \
+    "1: lwarx %0,0,%1" MUTEX_HINT_REL "\n"      \
     " subf. %0,%2,%0\n"      \
     " bne 2f\n"      \
     " stwcx. %3,0,%1\n"      \
diff -urN libc25-cvstip-20070126/sysdeps/powerpc/powerpc64/bits/atomic.h libc25/sysdeps/powerpc/powerpc64/bits/atomic.h
--- libc25-cvstip-20070126/sysdeps/powerpc/powerpc64/bits/atomic.h 2004-09-08 00:38:48.000000000 -0500
+++ libc25/sysdeps/powerpc/powerpc64/bits/atomic.h 2007-03-19 16:01:48.538170864 -0500
@@ -1,5 +1,5 @@
 /* Atomic operations.  PowerPC64 version.
-   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004, 2007 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
    Contributed by Paul Mackerras <[hidden email]>, 2003.
 
@@ -18,6 +18,22 @@
    Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
    02111-1307 USA.  */
 
+/*  POWER6 adds a "Mutex Hint" to the Load and Reserve instruction.
+    This is a hint to the hardware to expect additional updates adjacent
+    to the lock word or not.  If we are acquiring a Mutex, the hint
+    should be true. Otherwise we releasing a Mutex or doing a simple
+    atomic operation.  In that case we don't expect addtional updates
+    adjacent to the lock word after the Store Conditional and the hint
+    should be false.  */
+
+#if defined _ARCH_PWR6 || defined _ARCH_PWR6X
+#define MUTEX_HINT_ACQ ",1"
+#define MUTEX_HINT_REL ",0"
+#else
+#define MUTEX_HINT_ACQ
+#define MUTEX_HINT_REL
+#endif
+
 /* The 32-bit exchange_bool is different on powerpc64 because the subf
    does signed 64-bit arthmatic while the lwarx is 32-bit unsigned
    (a load word and zero (high 32) form) load.
@@ -28,7 +44,7 @@
 ({      \
   unsigned int __tmp, __tmp2;      \
   __asm __volatile ("   clrldi  %1,%1,32\n"      \
-    "1: lwarx %0,0,%2\n"      \
+    "1: lwarx %0,0,%2" MUTEX_HINT_ACQ "\n"      \
     " subf. %0,%1,%0\n"      \
     " bne 2f\n"      \
     " stwcx. %4,0,%2\n"      \
@@ -45,7 +61,7 @@
   unsigned int __tmp, __tmp2;      \
   __asm __volatile (__ARCH_REL_INSTR "\n"      \
     "   clrldi  %1,%1,32\n"      \
-    "1: lwarx %0,0,%2\n"      \
+    "1: lwarx %0,0,%2" MUTEX_HINT_REL "\n"      \
     " subf. %0,%1,%0\n"      \
     " bne 2f\n"      \
     " stwcx. %4,0,%2\n"      \
@@ -66,7 +82,7 @@
 ({      \
   unsigned long __tmp;      \
   __asm __volatile (      \
-    "1: ldarx %0,0,%1\n"      \
+    "1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n"      \
     " subf. %0,%2,%0\n"      \
     " bne 2f\n"      \
     " stdcx. %3,0,%1\n"      \
@@ -82,7 +98,7 @@
 ({      \
   unsigned long __tmp;      \
   __asm __volatile (__ARCH_REL_INSTR "\n"      \
-    "1: ldarx %0,0,%1\n"      \
+    "1: ldarx %0,0,%2" MUTEX_HINT_REL "\n"      \
     " subf. %0,%2,%0\n"      \
     " bne 2f\n"      \
     " stdcx. %3,0,%1\n"      \
@@ -99,7 +115,7 @@
       __typeof (*(mem)) __tmp;      \
       __typeof (mem)  __memp = (mem);      \
       __asm __volatile (      \
-        "1: ldarx %0,0,%1\n"      \
+        "1: ldarx %0,0,%1" MUTEX_HINT_ACQ "\n"      \
         " cmpd %0,%2\n"      \
         " bne 2f\n"      \
         " stdcx. %3,0,%1\n"      \
@@ -116,7 +132,7 @@
       __typeof (*(mem)) __tmp;      \
       __typeof (mem)  __memp = (mem);      \
       __asm __volatile (__ARCH_REL_INSTR "\n"      \
-        "1: ldarx %0,0,%1\n"      \
+        "1: ldarx %0,0,%1" MUTEX_HINT_REL "\n"      \
         " cmpd %0,%2\n"      \
         " bne 2f\n"      \
         " stdcx. %3,0,%1\n"      \
@@ -132,7 +148,7 @@
     ({      \
       __typeof (*mem) __val;      \
       __asm __volatile (__ARCH_REL_INSTR "\n"      \
- "1: ldarx %0,0,%2\n"      \
+ "1: ldarx %0,0,%2" MUTEX_HINT_ACQ "\n"      \
  " stdcx. %3,0,%2\n"      \
  " bne- 1b\n"      \
   " " __ARCH_ACQ_INSTR      \
@@ -146,7 +162,7 @@
     ({      \
       __typeof (*mem) __val;      \
       __asm __volatile (__ARCH_REL_INSTR "\n"      \
- "1: ldarx %0,0,%2\n"      \
+ "1: ldarx %0,0,%2" MUTEX_HINT_REL "\n"      \
  " stdcx. %3,0,%2\n"      \
  " bne- 1b"      \
  : "=&r" (__val), "=m" (*mem)      \
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Re: PPC add MUTEX_HINTS atomic ops for POWER6

Ulrich Drepper
Applied.

--
➧ Ulrich Drepper ➧ Red Hat, Inc. ➧ 444 Castro St ➧ Mountain View, CA ❖


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