[PATCH v2 0/4] x86: (not just) branch handling adjustments

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[PATCH v2 0/4] x86: (not just) branch handling adjustments

Jan Beulich-2
In the middle of addressing PR gas/24546 I've run into an issue
with a pre-existing test case, pointing out problems to be fixed
prior to being able to actually deal with the issues reported
there. In turn I've then noticed further issues, which the first
and the last two patches deal with.

1: x86: consolidate Disp<NN> handling a little
2: x86-64: fix Intel64 handling of branch with data16 prefix
3: x86-64: correct / adjust prefix emission
4: x86: adjust ignored prefix warning for branches

Jan
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[PATCH v2 1/4] x86: consolidate Disp<NN> handling a little

Jan Beulich-2
In memory operand addressing, which forms of displacement are permitted
besides Disp8 is pretty clearly limited
- outside of 64-bit mode, Disp16 or Disp32 only, depending on address
  size (MPX being special in not allowing Disp16),
- in 64-bit mode, Disp32s or Disp64 without address size override, and
  solely Disp32 with one.
Adjust assembler and i386-gen to match this, observing that templates
already get adjusted before trying to match them against input depending
on the presence of an address size prefix.

This adjustment logic gets extended to all cases, as certain DispNN
values should also be dropped when there's no such prefix. In fact
behavior of the assembler, perhaps besides the exact diagnostics wording,
should not differ between there being templates applicable to 64-bit and
non-64-bit at the same time, or there being fully separate sets of
templates, with their DispNN settings already reduced accordingly.

This adjustment logic further gets guarded such that there wouldn't be
and Disp<N> conversion based on address size prefix when this prefix
doesn't control the width of the displacement (on branches other than
absolute ones).

These adjustments then also allow folding two MOV templates, which had
been split between 64-bit and non-64-bits variants so far.

Once in this area also
- drop the bogus DispNN from JumpByte templates, leaving just the
  correct Disp8 there (compensated by i386_finalize_displacement()
  now setting Disp8 on their operands),
- add the missing Disp32S to XBEGIN.

Note that the changes make it necessary to temporarily mark a test as
XFAIL; this will get taken care of by a subsequent patch. The failing
parts are entirely bogus and will get replaced.

gas/
2019-12-XX  Jan Beulich  <[hidden email]>

        * config/tc-i386.c (i386_addressing_mode): Declare.
        (match_template): Don't transform displacement width flags for
        non-indirect branches. Re-write transformation logic.
        (i386_displacement): Also check BaseIndex when deciding whether
        an operand belongs to a direct branch. Restrict which DispNN get
        set.
        (i386_finalize_displacement): Set Disp8 for JumpByte templates.
        * config/tc-i386-intel.c (i386_intel_operand): Don't set Disp32
        for 64-bit addressing.
        * testsuite/gas/i386/i386.exp: XFail x86-64-branch-3.

opcodes/
2019-12-XX  Jan Beulich  <[hidden email]>

        * i386-gen.c (process_i386_operand_type): Don't set Disp32 for
        Cpu64 templates.
        * i386-opc.tbl (mov): Fold two templates.
        (jcxz, jecxz, jrcxz, loop, loope, loopne, loopnz, loopz): Drop
        Disp16, Disp32, and Disp32S.
        (xbegin): Add Disp32S.
        * i386-tbl.h: Re-generate.
---
v2: New, parts split off from later patch.

--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -939,12 +939,13 @@ i386_intel_operand (char *operand_string
 
   if (flag_code == CODE_64BIT)
     {
-      i.types[this_operand].bitfield.disp32 = 1;
       if (!i.prefix[ADDR_PREFIX])
  {
   i.types[this_operand].bitfield.disp64 = 1;
   i.types[this_operand].bitfield.disp32s = 1;
  }
+      else
+ i.types[this_operand].bitfield.disp32 = 1;
     }
   else if (!i.prefix[ADDR_PREFIX] ^ (flag_code == CODE_16BIT))
     i.types[this_operand].bitfield.disp32 = 1;
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -182,6 +182,7 @@ static char *parse_insn (char *, char *)
 static char *parse_operands (char *, const char *);
 static void swap_operands (void);
 static void swap_2_operands (int, int);
+static enum flag_code i386_addressing_mode (void);
 static void optimize_imm (void);
 static void optimize_disp (void);
 static const insn_template *match_template (char);
@@ -5883,51 +5884,50 @@ match_template (char mnem_suffix)
     break;
  }
 
-      /* Address size prefix will turn Disp64/Disp32/Disp16 operand
- into Disp32/Disp16/Disp32 operand.  */
-      if (i.prefix[ADDR_PREFIX] != 0)
-  {
-    /* There should be only one Disp operand.  */
-    switch (flag_code)
-    {
-    case CODE_16BIT:
-      for (j = 0; j < MAX_OPERANDS; j++)
- {
-  if (operand_types[j].bitfield.disp16)
-    {
-      addr_prefix_disp = j;
-      operand_types[j].bitfield.disp32 = 1;
-      operand_types[j].bitfield.disp16 = 0;
-      break;
-    }
- }
+      if (!t->opcode_modifier.jump
+  || t->opcode_modifier.jump == JUMP_ABSOLUTE)
+ {
+  /* There should be only one Disp operand.  */
+  for (j = 0; j < MAX_OPERANDS; j++)
+    if (operand_type_check (operand_types[j], disp))
       break;
-    case CODE_32BIT:
-      for (j = 0; j < MAX_OPERANDS; j++)
+  if (j < MAX_OPERANDS)
+    {
+      bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0);
+
+      addr_prefix_disp = j;
+
+      /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16
+ operand into Disp32/Disp32/Disp16/Disp32 operand.  */
+      switch (flag_code)
  {
-  if (operand_types[j].bitfield.disp32)
+ case CODE_16BIT:
+  override = !override;
+  /* Fall through.  */
+ case CODE_32BIT:
+  if (operand_types[j].bitfield.disp32
+      && operand_types[j].bitfield.disp16)
     {
-      addr_prefix_disp = j;
-      operand_types[j].bitfield.disp32 = 0;
-      operand_types[j].bitfield.disp16 = 1;
-      break;
+      operand_types[j].bitfield.disp16 = override;
+      operand_types[j].bitfield.disp32 = !override;
     }
- }
-      break;
-    case CODE_64BIT:
-      for (j = 0; j < MAX_OPERANDS; j++)
- {
-  if (operand_types[j].bitfield.disp64)
+  operand_types[j].bitfield.disp32s = 0;
+  operand_types[j].bitfield.disp64 = 0;
+  break;
+
+ case CODE_64BIT:
+  if (operand_types[j].bitfield.disp32s
+      || operand_types[j].bitfield.disp64)
     {
-      addr_prefix_disp = j;
-      operand_types[j].bitfield.disp64 = 0;
-      operand_types[j].bitfield.disp32 = 1;
-      break;
+      operand_types[j].bitfield.disp64 &= !override;
+      operand_types[j].bitfield.disp32s &= !override;
+      operand_types[j].bitfield.disp32 = override;
     }
+  operand_types[j].bitfield.disp16 = 0;
+  break;
  }
-      break;
     }
-  }
+ }
 
       /* Force 0x8b encoding for "mov foo@GOT, %eax".  */
       if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
@@ -9937,10 +9937,11 @@ i386_displacement (char *disp_start, cha
 
   operand_type_set (&bigdisp, 0);
   if (i.jumpabsolute
+      || i.types[this_operand].bitfield.baseindex
       || (current_templates->start->opcode_modifier.jump != JUMP
   && current_templates->start->opcode_modifier.jump != JUMP_DWORD))
     {
-      bigdisp.bitfield.disp32 = 1;
+      i386_addressing_mode ();
       override = (i.prefix[ADDR_PREFIX] != 0);
       if (flag_code == CODE_64BIT)
  {
@@ -9949,12 +9950,13 @@ i386_displacement (char *disp_start, cha
       bigdisp.bitfield.disp32s = 1;
       bigdisp.bitfield.disp64 = 1;
     }
+  else
+    bigdisp.bitfield.disp32 = 1;
  }
       else if ((flag_code == CODE_16BIT) ^ override)
- {
-  bigdisp.bitfield.disp32 = 0;
   bigdisp.bitfield.disp16 = 1;
- }
+      else
+  bigdisp.bitfield.disp32 = 1;
     }
   else
     {
@@ -9966,10 +9968,7 @@ i386_displacement (char *disp_start, cha
   if (override || i.suffix == WORD_MNEM_SUFFIX)
     bigdisp.bitfield.disp16 = 1;
   else
-    {
-      bigdisp.bitfield.disp32 = 1;
-      bigdisp.bitfield.disp32s = 1;
-    }
+    bigdisp.bitfield.disp32s = 1;
  }
       else
  {
@@ -10142,6 +10141,11 @@ i386_finalize_displacement (segT exp_seg
     }
 #endif
 
+  if (current_templates->start->opcode_modifier.jump == JUMP_BYTE
+      /* Constants get taken care of by optimize_disp().  */
+      && exp->X_op != O_constant)
+    i.types[this_operand].bitfield.disp8 = 1;
+
   /* Check if this is a displacement only operand.  */
   bigdisp = i.types[this_operand];
   bigdisp.bitfield.disp8 = 0;
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1124,6 +1124,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
 
  run_dump_test "x86-64-jump"
  run_dump_test "x86-64-branch-2"
+ setup_xfail "*-*-*"
  run_list_test "x86-64-branch-3" "-al -mintel64"
  run_list_test "x86-64-branch-4" "-al -mintel64"
 
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -1236,7 +1236,8 @@ process_i386_operand_type (FILE *table,
   if (!active_cpu_flags.bitfield.cpu64
       && !active_cpu_flags.bitfield.cpumpx)
     set_bitfield("Disp16", types, 1, ARRAY_SIZE (types), lineno);
-  set_bitfield("Disp32", types, 1, ARRAY_SIZE (types), lineno);
+  if (!active_cpu_flags.bitfield.cpu64)
+    set_bitfield("Disp32", types, 1, ARRAY_SIZE (types), lineno);
   if (!active_cpu_flags.bitfield.cpuno64)
     set_bitfield("Disp32S", types, 1, ARRAY_SIZE (types), lineno);
  }
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -90,10 +90,7 @@
 ### MARKER ###
 
 // Move instructions.
-// We put the 64bit displacement first and we only mark constants
-// larger than 32bit as Disp64.
-mov, 2, 0xa0, None, 1, Cpu64, D|W|No_sSuf|No_ldSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
-mov, 2, 0xa0, None, 1, CpuNo64, D|W|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
+mov, 2, 0xa0, None, 1, 0, D|W|No_sSuf|No_qSuf|No_ldSuf, { Disp16|Disp32|Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
 mov, 2, 0x88, None, 1, 0, D|W|CheckRegSize|Modrm|No_sSuf|No_ldSuf|HLEPrefixOk=3, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
 // In the 64bit mode the short form mov immediate is redefined to have
 // 64bit value.
@@ -447,24 +444,24 @@ jnle, 1, 0x7f, None, 1, 0, Jump|No_bSuf|
 jg, 1, 0x7f, None, 1, 0, Jump|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|BNDPrefixOk, { Disp8|Disp16|Disp32|Disp32S }
 
 // jcxz vs. jecxz is chosen on the basis of the address size prefix.
-jcxz, 1, 0xe3, None, 1, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-jecxz, 1, 0xe3, None, 1, 0, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32|Disp32S }
-jrcxz, 1, 0xe3, None, 1, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
+jcxz, 1, 0xe3, None, 1, CpuNo64, JumpByte|Size16|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
+jecxz, 1, 0xe3, None, 1, 0, JumpByte|Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
+jrcxz, 1, 0xe3, None, 1, Cpu64, JumpByte|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp8 }
 
 // The loop instructions also use the address size prefix to select
 // %cx rather than %ecx for the loop count, so the `w' form of these
 // instructions emit an address size prefix rather than a data size
 //  prefix.
-loop, 1, 0xe2, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loop, 1, 0xe2, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loopz, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopz, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loope, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loope, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loopnz, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopnz, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
-loopne, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8|Disp16|Disp32 }
-loopne, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8|Disp32|Disp32S }
+loop, 1, 0xe2, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
+loop, 1, 0xe2, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
+loopz, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
+loopz, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
+loope, 1, 0xe1, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
+loope, 1, 0xe1, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
+loopnz, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
+loopnz, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
+loopne, 1, 0xe0, None, 1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp8 }
+loopne, 1, 0xe0, None, 1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Disp8 }
 
 // Set byte on flag instructions.
 seto, 1, 0xf90, 0x0, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex }
@@ -2552,7 +2549,7 @@ xrelease, 0, 0xf3, None, 1, CpuHLE, No_b
 
 // RTM instructions
 xabort, 1, 0xc6f8, None, 2, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 }
-xbegin, 1, 0xc7f8, None, 2, CpuRTM,  JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32 }
+xbegin, 1, 0xc7f8, None, 2, CpuRTM,  JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Disp16|Disp32|Disp32S }
 xend, 0, 0xf01d5, None, 3, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 xtest, 0, 0xf01d6, None, 3, CpuHLE|CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 

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[PATCH v2 2/4] x86-64: fix Intel64 handling of branch with data16 prefix

Jan Beulich-2
In reply to this post by Jan Beulich-2
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious
direct destination to translate to an indirect _far_ branch is plain
wrong. The operand size prefix should have no effect at all on the
interpretation of the operand. The main underlying issue here is that
the Intel64 templates of the direct branches don't include Disp16, yet
various assumptions exist that it would always be there when there's
also Disp32/Disp32S, toggled by the operand size prefix (which is
being ignored by direct branches in Intel64 mode).

Along these lines it was also wrong to base the displacement width
decision solely on the operand size prefix: REX.W cancels this effect
and hence needs taking into consideration, too.

A disassembler change is needed here as well: XBEGIN was wrongly treated
the same as direct CALL/JMP, which isn't the case - the operand size
prefix does affect displacement size there, it's merely ignored when it
comes to updating [ER]IP.

gas/
2019-12-XX  Jan Beulich  <[hidden email]>

        * config/tc-i386.c (flip_code16): New.
        (output_branch, output_jump): Use it.
        (i386_displacement): Restrict template set to just direct
        branches when handling a respective operand. Don't set Disp16
        when in Intel64 mode and there's a respective template.
        * testsuite/gas/i386/i386.exp: Convert x86-64-branch-3 from list
        to dump test. Drop its XFail again.
        * testsuite/gas/i386/x86-64-branch-3.d: New.
        * testsuite/gas/i386/x86-64-branch-3.l: Delete.
        * testsuite/gas/i386/x86-64-branch-3.s: Add XBEGIN case.

opcodes/
2019-12-XX  Jan Beulich  <[hidden email]>

        * i386-dis.c (Jdqw): Define.
        (dqw_mode): Adjust associated comment.
        (rm_table): Use Jdqw for XBEGIN.
        (OP_J): Handle dqw_mode.
---
v2: Split not directly related DispNN handling adjustments into prereq
    patch.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7861,6 +7861,18 @@ build_modrm_byte (void)
   return default_seg;
 }
 
+static unsigned int
+flip_code16 (unsigned int code16)
+{
+  gas_assert (i.tm.operands == 1);
+
+  return !(i.prefix[REX_PREFIX] & REX_W)
+ && (code16 ? i.tm.operand_types[0].bitfield.disp32
+      || i.tm.operand_types[0].bitfield.disp32s
+    : i.tm.operand_types[0].bitfield.disp16)
+ ? CODE16 : 0;
+}
+
 static void
 output_branch (void)
 {
@@ -7880,7 +7892,7 @@ output_branch (void)
     {
       prefix = 1;
       i.prefixes -= 1;
-      code16 ^= CODE16;
+      code16 ^= flip_code16(code16);
     }
   /* Pentium4 branch hints.  */
   if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
@@ -8022,7 +8034,7 @@ output_jump (void)
  {
   FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
   i.prefixes -= 1;
-  code16 ^= CODE16;
+  code16 ^= flip_code16(code16);
  }
 
       size = 4;
@@ -9960,12 +9972,34 @@ i386_displacement (char *disp_start, cha
     }
   else
     {
-      /* For PC-relative branches, the width of the displacement
- is dependent upon data size, not address size.  */
+      /* For PC-relative branches, the width of the displacement may be
+ dependent upon data size, but is never dependent upon address size.
+ Also make sure to not unintentionally match against a non-PC-relative
+ branch template.  */
+      static templates aux_templates;
+      const insn_template *t = current_templates->start;
+      bfd_boolean has_intel64 = FALSE;
+
+      aux_templates.start = t;
+      while (++t < current_templates->end)
+ {
+  if (t->opcode_modifier.jump
+      != current_templates->start->opcode_modifier.jump)
+    break;
+  if (t->opcode_modifier.intel64)
+    has_intel64 = TRUE;
+ }
+      if (t < current_templates->end)
+ {
+  aux_templates.end = t;
+  current_templates = &aux_templates;
+ }
+
       override = (i.prefix[DATA_PREFIX] != 0);
       if (flag_code == CODE_64BIT)
  {
-  if (override || i.suffix == WORD_MNEM_SUFFIX)
+  if ((override || i.suffix == WORD_MNEM_SUFFIX)
+      && (!intel64 || !has_intel64))
     bigdisp.bitfield.disp16 = 1;
   else
     bigdisp.bitfield.disp32s = 1;
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1124,8 +1124,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
 
  run_dump_test "x86-64-jump"
  run_dump_test "x86-64-branch-2"
- setup_xfail "*-*-*"
- run_list_test "x86-64-branch-3" "-al -mintel64"
+ run_dump_test "x86-64-branch-3"
  run_list_test "x86-64-branch-4" "-al -mintel64"
 
  run_dump_test "x86-64-gotpcrel"
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.d
@@ -0,0 +1,16 @@
+#as: -J -mintel64
+#objdump: -dwr -Mintel64
+#name: x86-64 branch 3
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <bar-0x6>:
+[ ]*[a-f0-9]+: 66 e9 00 00 00 00     data16 jmpq 6 <bar> 2: R_X86_64_PLT32 foo-0x4
+
+0+6 <bar>:
+[ ]*[a-f0-9]+: 89 c3                 mov    %eax,%ebx
+[ ]*[a-f0-9]+: 66 e8 00 00 00 00     data16 callq e <bar\+0x8> a: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 66 c7 f8 00 00       xbeginw 13 <bar\+0xd> 11: R_X86_64_PC16 foo-0x2
+#pass
--- a/gas/testsuite/gas/i386/x86-64-branch-3.l
+++ /dev/null
@@ -1,17 +0,0 @@
-.*: Assembler messages:
-.*:2: Warning: indirect jmp without `\*'
-.*:7: Warning: indirect call without `\*'
-GAS LISTING .*
-
-
-[ ]*1[ ]+\.text
-[ ]*2[ ]+0000 66FF2C25 data16 jmp foo
-\*\*\*\*  Warning: indirect jmp without `\*'
-[ ]*2[ ]+00000000
-[ ]*3[ ]+
-[ ]*4[ ]+bar:
-[ ]*5[ ]+0008 89C3     mov %eax, %ebx
-[ ]*6[ ]+
-[ ]*7[ ]+000a 66FF1C25 data16 call foo
-\*\*\*\*  Warning: indirect call without `\*'
-[ ]*7[ ]+00000000
--- a/gas/testsuite/gas/i386/x86-64-branch-3.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.s
@@ -5,3 +5,5 @@ bar:
  mov %eax, %ebx
 
  data16 call foo
+
+ data16 xbegin foo
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -297,6 +297,7 @@ fetch_data (struct disassemble_info *inf
 #define I1 { OP_I, const_1_mode }
 #define Jb { OP_J, b_mode }
 #define Jv { OP_J, v_mode }
+#define Jdqw { OP_J, dqw_mode }
 #define Cm { OP_C, m_mode }
 #define Dm { OP_D, m_mode }
 #define Td { OP_T, d_mode }
@@ -560,7 +561,8 @@ enum
   v_bndmk_mode,
   /* operand size depends on REX prefixes.  */
   dq_mode,
-  /* registers like dq_mode, memory like w_mode.  */
+  /* registers like dq_mode, memory like w_mode, displacements like
+     v_mode without considering Intel64 ISA.  */
   dqw_mode,
   /* bounds operand */
   bnd_mode,
@@ -10971,7 +10973,7 @@ static const struct dis386 rm_table[][8]
   },
   {
     /* RM_C7_REG_7 */
-    { "xbeginT", { Skip_MODRM, Jv }, 0 },
+    { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
   },
   {
     /* RM_0F01_REG_0 */
@@ -14830,10 +14832,12 @@ OP_J (int bytemode, int sizeflag)
       break;
     case v_mode:
       if (isa64 != intel64)
+    case dqw_mode:
  USED_REX (REX_W);
       if ((sizeflag & DFLAG)
   || (address_mode == mode_64bit
-      && (isa64 == intel64 || (rex & REX_W))))
+      && ((isa64 == intel64 && bytemode != dqw_mode)
+  || (rex & REX_W))))
  disp = get32s ();
       else
  {

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[PATCH v2 3/4] x86-64: correct / adjust prefix emission

Jan Beulich-2
In reply to this post by Jan Beulich-2
First and foremost REX must come last. Next JumpInterSegment branches
can't possibly have a REX prefix, as they're consistently CpuNo64. And
finally make BND prefix handling in output_branch() consistent with that
of other prefixes in the same function, and make its placement among
prefixes consistent with output_jump() (which, oddly enough, still isn't
the supposedly canonical order specified by the *_PREFIX definitions).

gas/
2019-12-XX  Jan Beulich  <[hidden email]>

        * config/tc-i386.c (output_branch): Handle BND prefix the same
        way as other prefixes. Emit it last before REX.
        (output_jump): Emit BND before REX.
        (output_interseg_jump): Don't emit REX.
        * testsuite/gas/i386/x86-64-branch-2.s,
        testsuite/gas/i386/x86-64-branch-3.s,
        testsuite/gas/i386/x86-64-mpx-branch-1.s,
        testsuite/gas/i386/x86-64-mpx-branch-2.s: Add REX.W cases.
        * testsuite/gas/i386/x86-64-mpx-branch-2.d: Match output against
        x86-64-mpx-branch-1.d.
        * testsuite/gas/i386/x86-64-branch-2.d,
        testsuite/gas/i386/x86-64-branch-3.d,
        testsuite/gas/i386/x86-64-mpx-branch-1.d: Adjust expectations.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7910,8 +7910,8 @@ output_branch (void)
   /* BND prefixed jump.  */
   if (i.prefix[BND_PREFIX] != 0)
     {
-      FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
-      i.prefixes -= 1;
+      prefix++;
+      i.prefixes--;
     }
 
   if (i.prefixes != 0 && !intel_syntax)
@@ -7930,6 +7930,8 @@ output_branch (void)
   if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
       || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
     *p++ = i.prefix[SEG_PREFIX];
+  if (i.prefix[BND_PREFIX] != 0)
+    *p++ = BND_PREFIX_OPCODE;
   if (i.prefix[REX_PREFIX] != 0)
     *p++ = i.prefix[REX_PREFIX];
   *p = i.tm.base_opcode;
@@ -8042,16 +8044,16 @@ output_jump (void)
  size = 2;
     }
 
-  if (i.prefix[REX_PREFIX] != 0)
+  /* BND prefixed jump.  */
+  if (i.prefix[BND_PREFIX] != 0)
     {
-      FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
+      FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
       i.prefixes -= 1;
     }
 
-  /* BND prefixed jump.  */
-  if (i.prefix[BND_PREFIX] != 0)
+  if (i.prefix[REX_PREFIX] != 0)
     {
-      FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
+      FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
       i.prefixes -= 1;
     }
 
@@ -8109,11 +8111,8 @@ output_interseg_jump (void)
       i.prefixes -= 1;
       code16 ^= CODE16;
     }
-  if (i.prefix[REX_PREFIX] != 0)
-    {
-      prefix++;
-      i.prefixes -= 1;
-    }
+
+  gas_assert (!i.prefix[REX_PREFIX]);
 
   size = 4;
   if (code16)
--- a/gas/testsuite/gas/i386/x86-64-branch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.d
@@ -6,10 +6,12 @@
 
 Disassembly of section .text:
 
-0+ <bar-0x4>:
-[ ]*[a-f0-9]+: 66 e9 00 00           jmpw   4 <bar> 2: R_X86_64_PC16 foo-0x2
+0+ <bar-0xb>:
+[ ]*[a-f0-9]+: 66 e9 00 00           jmpw   4 <bar-0x7> 2: R_X86_64_PC16 foo-0x2
+[ ]*[a-f0-9]+: 66 48 e9 00 00 00 00 data16 jmpq b <bar> 7: R_X86_64_PLT32 foo-0x4
 
-0+4 <bar>:
+0+b <bar>:
 [ ]*[a-f0-9]+: 89 c3                 mov    %eax,%ebx
-[ ]*[a-f0-9]+: 66 e8 00 00           callw  a <bar\+0x6> 8: R_X86_64_PC16 foo-0x2
+[ ]*[a-f0-9]+: 66 e8 00 00           callw  11 <bar\+0x6> f: R_X86_64_PC16 foo-0x2
+[ ]*[a-f0-9]+: 66 48 e8 00 00 00 00 data16 callq 18 <bar\+0xd> 14: R_X86_64_PLT32 foo-0x4
 #pass
--- a/gas/testsuite/gas/i386/x86-64-branch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.s
@@ -1,7 +1,9 @@
  .text
  data16 jmp foo
+ data16 rex.w jmp foo
 
 bar:
  mov %eax, %ebx
 
  data16 call foo
+ data16 rex.w call foo
--- a/gas/testsuite/gas/i386/x86-64-branch-3.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.d
@@ -6,11 +6,14 @@
 
 Disassembly of section .text:
 
-0+ <bar-0x6>:
-[ ]*[a-f0-9]+: 66 e9 00 00 00 00     data16 jmpq 6 <bar> 2: R_X86_64_PLT32 foo-0x4
+0+ <bar-0xd>:
+[ ]*[a-f0-9]+: 66 e9 00 00 00 00     data16 jmpq 6 <bar-0x7> 2: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 66 48 e9 00 00 00 00 data16 rex\.W jmpq d <bar> 9: R_X86_64_PLT32 foo-0x4
 
-0+6 <bar>:
+0+d <bar>:
 [ ]*[a-f0-9]+: 89 c3                 mov    %eax,%ebx
-[ ]*[a-f0-9]+: 66 e8 00 00 00 00     data16 callq e <bar\+0x8> a: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: 66 c7 f8 00 00       xbeginw 13 <bar\+0xd> 11: R_X86_64_PC16 foo-0x2
+[ ]*[a-f0-9]+: 66 e8 00 00 00 00     data16 callq 15 <bar\+0x8> 11: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 66 48 e8 00 00 00 00 data16 rex\.W callq 1c <bar\+0xf> 18: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 66 c7 f8 00 00       xbeginw 21 <bar\+0x14> 1f: R_X86_64_PC16 foo-0x2
+[ ]*[a-f0-9]+: 66 48 c7 f8 00 00 00 00 data16 xbeginq 29 <bar\+0x1c> 25: R_X86_64_PLT32 foo-0x4
 #pass
--- a/gas/testsuite/gas/i386/x86-64-branch-3.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.s
@@ -1,9 +1,12 @@
  .text
  data16 jmp foo
+ data16 rex.w jmp foo
 
 bar:
  mov %eax, %ebx
 
  data16 call foo
+ data16 rex.w call foo
 
  data16 xbegin foo
+ data16 rex.w xbegin foo
--- a/gas/testsuite/gas/i386/x86-64-mpx-branch-1.d
+++ b/gas/testsuite/gas/i386/x86-64-mpx-branch-1.d
@@ -8,22 +8,24 @@
 
 Disassembly of section .text:
 
-0+ <foo1-0xc>:
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 6 <foo1-0x6> 2: R_X86_64_PC32 \*ABS\*\+0x10003c
-[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq c <foo1> 8: R_X86_64_PC32 \*ABS\*\+0x10003c
+0+ <foo1-0x1c>:
+[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 6 <foo1-0x16> 2: R_X86_64_PC32 \*ABS\*\+0x10003c
+[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq c <foo1-0x10> 8: R_X86_64_PC32 \*ABS\*\+0x10003c
+[ ]*[a-f0-9]+: 66 f2 48 e8 00 00 00 00 data16 bnd callq 14 <foo1-0x8> 10: R_X86_64_PC32 \*ABS\*\+0x10003c
+[ ]*[a-f0-9]+: 66 f2 48 e9 00 00 00 00 data16 bnd jmpq 1c <foo1> 18: R_X86_64_PC32 \*ABS\*\+0x10003c
 
-0+c <foo1>:
-[ ]*[a-f0-9]+: f2 eb fd             bnd jmp c <foo1>
-[ ]*[a-f0-9]+: f2 72 fa             bnd jb c <foo1>
-[ ]*[a-f0-9]+: f2 e8 f4 ff ff ff     bnd callq c <foo1>
-[ ]*[a-f0-9]+: f2 eb 09             bnd jmp 24 <foo2>
-[ ]*[a-f0-9]+: f2 72 06             bnd jb 24 <foo2>
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 24 <foo2>
+0+1c <foo1>:
+[ ]*[a-f0-9]+: f2 eb fd             bnd jmp 1c <foo1>
+[ ]*[a-f0-9]+: f2 72 fa             bnd jb 1c <foo1>
+[ ]*[a-f0-9]+: f2 e8 f4 ff ff ff     bnd callq 1c <foo1>
+[ ]*[a-f0-9]+: f2 eb 09             bnd jmp 34 <foo2>
+[ ]*[a-f0-9]+: f2 72 06             bnd jb 34 <foo2>
+[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 34 <foo2>
 
-0+24 <foo2>:
-[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq 2a <foo2\+0x6> 26: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 0f 82 00 00 00 00 bnd jb 31 <foo2\+0xd> 2d: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 37 <foo2\+0x13> 33: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq 3d <foo2\+0x19> 39: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 0f 82 00 00 00 00 bnd jb 44 <foo2\+0x20> 40: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 4a <foo2\+0x26> 46: R_X86_64_PLT32 foo-0x4
+0+34 <foo2>:
+[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq 3a <foo2\+0x6> 36: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: f2 0f 82 00 00 00 00 bnd jb 41 <foo2\+0xd> 3d: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 47 <foo2\+0x13> 43: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq 4d <foo2\+0x19> 49: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: f2 0f 82 00 00 00 00 bnd jb 54 <foo2\+0x20> 50: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 5a <foo2\+0x26> 56: R_X86_64_PLT32 foo-0x4
--- a/gas/testsuite/gas/i386/x86-64-mpx-branch-1.s
+++ b/gas/testsuite/gas/i386/x86-64-mpx-branch-1.s
@@ -2,6 +2,9 @@
  bnd call 0x100040
  bnd jmp 0x100040
 
+ bnd data16 rex.w call 0x100040
+ bnd data16 rex.w jmp 0x100040
+
 foo1:
  bnd jmp foo1
  bnd jb foo1
--- a/gas/testsuite/gas/i386/x86-64-mpx-branch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-mpx-branch-2.d
@@ -1,29 +1,5 @@
 #as: -J -madd-bnd-prefix
 #objdump: -dwr
 #name: x86-64 branch with BND prefix
+#dump: x86-64-mpx-branch-1.d
 #notarget: *-*-solaris*
-
-.*: +file format .*
-
-
-Disassembly of section .text:
-
-0+ <foo1-0xc>:
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 6 <foo1-0x6> 2: R_X86_64_PC32 \*ABS\*\+0x10003c
-[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq c <foo1> 8: R_X86_64_PC32 \*ABS\*\+0x10003c
-
-0+c <foo1>:
-[ ]*[a-f0-9]+: f2 eb fd             bnd jmp c <foo1>
-[ ]*[a-f0-9]+: f2 72 fa             bnd jb c <foo1>
-[ ]*[a-f0-9]+: f2 e8 f4 ff ff ff     bnd callq c <foo1>
-[ ]*[a-f0-9]+: f2 eb 09             bnd jmp 24 <foo2>
-[ ]*[a-f0-9]+: f2 72 06             bnd jb 24 <foo2>
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 24 <foo2>
-
-0+24 <foo2>:
-[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq 2a <foo2\+0x6> 26: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 0f 82 00 00 00 00 bnd jb 31 <foo2\+0xd> 2d: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 37 <foo2\+0x13> 33: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 e9 00 00 00 00     bnd jmpq 3d <foo2\+0x19> 39: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 0f 82 00 00 00 00 bnd jb 44 <foo2\+0x20> 40: R_X86_64_PLT32 foo-0x4
-[ ]*[a-f0-9]+: f2 e8 00 00 00 00     bnd callq 4a <foo2\+0x26> 46: R_X86_64_PLT32 foo-0x4
--- a/gas/testsuite/gas/i386/x86-64-mpx-branch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-mpx-branch-2.s
@@ -2,6 +2,9 @@
  call 0x100040
  jmp 0x100040
 
+ data16 rex.w call 0x100040
+ data16 rex.w jmp 0x100040
+
 foo1:
  jmp foo1
  jb foo1

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[PATCH v2 4/4] x86: adjust ignored prefix warning for branches

Jan Beulich-2
In reply to this post by Jan Beulich-2
There's no reason to not also issue them in Intel syntax mode, and it
can be quite helpful to mention the actual insn (after all there can be
multiple on a single line).

gas/
2019-12-XX  Jan Beulich  <[hidden email]>

        * config/tc-i386.c (output_branch, output_jump,
        output_interseg_jump): Also emit skipped prefix warning in Intel
        syntax mode. Name instruction in the warning text.
        * testsuite/gas/i386/mpx-inval-1.l,
        testsuite/gas/i386/notrackbad.l,
        testsuite/gas/i386/x86-64-notrackbad.l: Adjust expectations.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -7914,8 +7914,8 @@ output_branch (void)
       i.prefixes--;
     }
 
-  if (i.prefixes != 0 && !intel_syntax)
-    as_warn (_("skipping prefixes on this instruction"));
+  if (i.prefixes != 0)
+    as_warn (_("skipping prefixes on `%s'"), i.tm.name);
 
   /* It's always a symbol;  End frag & setup for relax.
      Make sure there is enough room in this frag for the largest
@@ -8057,8 +8057,8 @@ output_jump (void)
       i.prefixes -= 1;
     }
 
-  if (i.prefixes != 0 && !intel_syntax)
-    as_warn (_("skipping prefixes on this instruction"));
+  if (i.prefixes != 0)
+    as_warn (_("skipping prefixes on `%s'"), i.tm.name);
 
   p = frag_more (i.tm.opcode_length + size);
   switch (i.tm.opcode_length)
@@ -8118,8 +8118,8 @@ output_interseg_jump (void)
   if (code16)
     size = 2;
 
-  if (i.prefixes != 0 && !intel_syntax)
-    as_warn (_("skipping prefixes on this instruction"));
+  if (i.prefixes != 0)
+    as_warn (_("skipping prefixes on `%s'"), i.tm.name);
 
   /* 1 opcode; 2 segment; offset  */
   p = frag_more (prefix + 1 + 2 + size);
--- a/gas/testsuite/gas/i386/mpx-inval-1.l
+++ b/gas/testsuite/gas/i386/mpx-inval-1.l
@@ -2,15 +2,17 @@
 .*:6: Error: expecting valid branch instruction after `bnd'
 .*:7: Error: expecting valid branch instruction after `bnd'
 .*:8: Error: expecting valid branch instruction after `bnd'
-.*:8: Warning: skipping prefixes on this instruction
+.*:8: Warning: skipping prefixes on `lcall'
 .*:9: Error: expecting valid branch instruction after `bnd'
-.*:9: Warning: skipping prefixes on this instruction
+.*:9: Warning: skipping prefixes on `ljmp'
 .*:10: Error: expecting valid branch instruction after `bnd'
 .*:11: Error: expecting valid branch instruction after `bnd'
 .*:14: Error: expecting valid branch instruction after `bnd'
 .*:15: Error: expecting valid branch instruction after `bnd'
 .*:16: Error: expecting valid branch instruction after `bnd'
+.*:16: Warning: skipping prefixes on `lcall'
 .*:17: Error: expecting valid branch instruction after `bnd'
+.*:17: Warning: skipping prefixes on `ljmp'
 .*:18: Error: expecting valid branch instruction after `bnd'
 .*:19: Error: expecting valid branch instruction after `bnd'
 GAS LISTING .*
@@ -27,11 +29,11 @@ GAS LISTING .*
 .*  Error: expecting valid branch instruction after `bnd'
 [ ]*8[ ]+\?\?\?\? 9A000000 bnd lcall \$0x1234,\$xxx
 .*  Error: expecting valid branch instruction after `bnd'
-.*  Warning: skipping prefixes on this instruction
+.*  Warning: skipping prefixes on `lcall'
 [ ]*8[ ]+003412
 [ ]*9[ ]+\?\?\?\? EA000000 bnd ljmp \$0x1234,\$xxx
 .*  Error: expecting valid branch instruction after `bnd'
-.*  Warning: skipping prefixes on this instruction
+.*  Warning: skipping prefixes on `ljmp'
 [ ]*9[ ]+003412
 [ ]*10[ ]+\?\?\?\? F2E2E9   bnd loop foo
 .*  Error: expecting valid branch instruction after `bnd'
@@ -45,9 +47,11 @@ GAS LISTING .*
 .*  Error: expecting valid branch instruction after `bnd'
 [ ]*16[ ]+\?\?\?\? 9A000000 bnd lcall 0x1234,xxx
 .*  Error: expecting valid branch instruction after `bnd'
+.*  Warning: skipping prefixes on `lcall'
 [ ]*16[ ]+003412
 [ ]*17[ ]+\?\?\?\? EA000000 bnd ljmp 0x1234,xxx
 .*  Error: expecting valid branch instruction after `bnd'
+.*  Warning: skipping prefixes on `ljmp'
 [ ]*17[ ]+003412
 [ ]*18[ ]+\?\?\?\? F2E2CE   bnd loop foo
 .*  Error: expecting valid branch instruction after `bnd'
--- a/gas/testsuite/gas/i386/notrackbad.l
+++ b/gas/testsuite/gas/i386/notrackbad.l
@@ -1,6 +1,6 @@
 .*: Assembler messages:
 .*:6: Error: expecting indirect branch instruction after `notrack'
-.*:6: Warning: skipping prefixes on this instruction
+.*:6: Warning: skipping prefixes on `call'
 .*:7: Error: expecting indirect branch instruction after `notrack'
 .*:9: Error: same type of prefix used twice
 .*:10: Error: same type of prefix used twice
@@ -16,7 +16,7 @@ GAS LISTING .*
 [ ]*5[ ]+_start:
 [ ]*6[ ]+\?\?\?\? [0-9A-F]* notrack call foo
 \*\*\*\*  Error: expecting indirect branch instruction after `notrack'
-\*\*\*\*  Warning: skipping prefixes on this instruction
+\*\*\*\*  Warning: skipping prefixes on `call'
 [ ]*6[ ]+[0-9A-F]*
 [ ]*7[ ]+\?\?\?\? [0-9A-F]* notrack jmp foo
 \*\*\*\*  Error: expecting indirect branch instruction after `notrack'
--- a/gas/testsuite/gas/i386/x86-64-notrackbad.l
+++ b/gas/testsuite/gas/i386/x86-64-notrackbad.l
@@ -1,6 +1,6 @@
 .*: Assembler messages:
 .*:6: Error: expecting indirect branch instruction after `notrack'
-.*:6: Warning: skipping prefixes on this instruction
+.*:6: Warning: skipping prefixes on `call'
 .*:7: Error: expecting indirect branch instruction after `notrack'
 .*:9: Error: same type of prefix used twice
 .*:10: Error: same type of prefix used twice
@@ -16,7 +16,7 @@ GAS LISTING .*
 [ ]*5[ ]+_start:
 [ ]*6[ ]+\?\?\?\? [0-9A-F]* notrack call foo
 \*\*\*\*  Error: expecting indirect branch instruction after `notrack'
-\*\*\*\*  Warning: skipping prefixes on this instruction
+\*\*\*\*  Warning: skipping prefixes on `call'
 [ ]*6[ ]+[0-9A-F]*
 [ ]*7[ ]+\?\?\?\? [0-9A-F]* notrack jmp foo
 \*\*\*\*  Error: expecting indirect branch instruction after `notrack'

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Re: [PATCH v2 0/4] x86: (not just) branch handling adjustments

H.J. Lu-30
In reply to this post by Jan Beulich-2
Ok for all.

Thanks.

On Mon, Dec 23, 2019, 8:01 AM Jan Beulich <[hidden email]> wrote:

> In the middle of addressing PR gas/24546 I've run into an issue
> with a pre-existing test case, pointing out problems to be fixed
> prior to being able to actually deal with the issues reported
> there. In turn I've then noticed further issues, which the first
> and the last two patches deal with.
>
> 1: x86: consolidate Disp<NN> handling a little
> 2: x86-64: fix Intel64 handling of branch with data16 prefix
> 3: x86-64: correct / adjust prefix emission
> 4: x86: adjust ignored prefix warning for branches
>
> Jan
>
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Re: [PATCH v2 0/4] x86: (not just) branch handling adjustments

Jan Beulich-2
On 23.12.2019 14:54, H.J. Lu wrote:
> Ok for all.

Thanks. FTR - I had to rebase this ahead of
https://sourceware.org/ml/binutils/2019-11/msg00349.html
for it to apply. I did previously ping this still pending
patch.

Jan

> On Mon, Dec 23, 2019, 8:01 AM Jan Beulich <[hidden email]> wrote:
>
>> In the middle of addressing PR gas/24546 I've run into an issue
>> with a pre-existing test case, pointing out problems to be fixed
>> prior to being able to actually deal with the issues reported
>> there. In turn I've then noticed further issues, which the first
>> and the last two patches deal with.
>>
>> 1: x86: consolidate Disp<NN> handling a little
>> 2: x86-64: fix Intel64 handling of branch with data16 prefix
>> 3: x86-64: correct / adjust prefix emission
>> 4: x86: adjust ignored prefix warning for branches
>>
>> Jan
>>
>