[PATCH] [SPARC] Get the sparc32 cpus working with latest cgen.

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[PATCH] [SPARC] Get the sparc32 cpus working with latest cgen.

Jose E. Marchesi

Hi.

Well, here is my first patch.  Please take it cautiously since I am
pretty new to CGEN :)

This patch fixes the generation of the sparc32 cpus, which is currently
broken.  The sparcfpu.cpu file was implementing the fp registers as
integer values using the mode SI while the operands fr* are declared to
be of type SF or DF.  This was causing an assertion in rtx-operand-obj
to fail, since it makes sure that the mode declared in the operand
matches the mode of the corresponding hardware.

Note that I did not compile the generated code yet (still working in the
sim files) but I made sure that all the subword and join variants used
in the generated code are properly defined in sim/common/cgen-ops.h, and
that the change in the register sets mode does not affect the generated
semantic routines in sem-*.c and the field extraction stuff in
decode*.c.

Note that the generation of the sparc64 cpus still don't work because of
other unrelated problem.

2012-01-22  Jose E. Marchesi  <[hidden email]>

        Get the sparc32 cpus working with latest cgen.
        * cpu/sparcfpu.cpu (h-fr32): Use SF values for storage.
        (h-fr64): Likewise.
        (h-frd32): Getter/setter adapted to the new physical registers.
        (h-frq32): Likewise.
        (h-frd64): Likewise.
        (h-frq64): Likewise.

Index: cpu/sparcfpu.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/sparcfpu.cpu,v
retrieving revision 1.1
diff -u -r1.1 sparcfpu.cpu
--- cpu/sparcfpu.cpu 5 Jul 2001 12:45:47 -0000 1.1
+++ cpu/sparcfpu.cpu 22 Jan 2012 12:21:09 -0000
@@ -9,11 +9,6 @@
 ; FP support is defined even for cpu's without an fpu as the instructions
 ; still have to be assembled and the simulator still has to recognize them
 ; so that the appropriate trap can be generated.
-;
-; The physical registers are stored as an array of SI values: here `SI'
-; denotes "set of 32 bits" rather than "32 bit signed integer".
-;
-; wip: currently evaluating the various possibilities
 
 ; Floating point hardware.
 
@@ -31,7 +26,7 @@
   (semantic-name h-fr)
   (comment "sparc32 floating point regs")
   (attrs (MACH32))
-  (type register SI (32))
+  (type register SF (32))
   (indices keyword "%" (.map build-freg-name (.iota 32)))
 )
 (define-hardware
@@ -39,7 +34,7 @@
   (semantic-name h-fr)
   (comment "sparc64 floating point regs")
   (attrs (MACH64))
-  (type register SI (64))
+  (type register SF (64))
   (indices keyword "%" (.map build-freg-name (.iota 64)))
 )
 
@@ -48,17 +43,17 @@
   (semantic-name h-frd)
   (comment "sparc32 double precision floating point regs")
   (attrs VIRTUAL (MACH32))
-  (type register DI (16))
+  (type register DF (16))
   ; ??? This works, but multiple copies of all the register names might be
   ; unpalatable.  Another way is to specify a register table plus a constraint.
   ;(indices keyword "%" (.map build-freg-name (.iota 16 0 2)))
-  (get (index) (join DI SI
-      (reg h-fr index)
-      (reg h-fr (add index 1))))
+  (get (index) (join DF SI
+      (subword SI (reg h-fr index) 0)
+      (subword SI (reg h-fr (add index 1)) 0)))
   (set (index newval)
        (sequence ()
- (set (reg h-fr index) (subword SI newval 0))
- (set (reg h-fr (add index 1)) (subword SI newval 1))))
+ (set (reg h-fr index) (subword SF (subword SI newval 0) 0))
+ (set (reg h-fr (add index 1)) (subword SF (subword SI newval 1) 0))))
 )
 
 (define-hardware
@@ -69,16 +64,16 @@
   (type register TF (8))
   (indices keyword "%" (.map build-freg-name (.iota 8 0 4)))
   (get (index) (join TF SI
-      (reg h-fr index)
-      (reg h-fr (add index (const 1)))
-      (reg h-fr (add index (const 2)))
-      (reg h-fr (add index (const 3)))))
+      (subword SI (reg h-fr index) 0)
+      (subword SI (reg h-fr (add index (const 1))) 0)
+      (subword SI (reg h-fr (add index (const 2))) 0)
+      (subword SI (reg h-fr (add index (const 3))) 0)))
   (set (index newval)
        (sequence ()
- (set (reg h-fr index) (subword SI newval 0))
- (set (reg h-fr (add index (const 1))) (subword SI newval 1))
- (set (reg h-fr (add index (const 2))) (subword SI newval 2))
- (set (reg h-fr (add index (const 3))) (subword SI newval 3))))
+ (set (reg h-fr index) (subword SF (subword SI newval 0) 0))
+ (set (reg h-fr (add index (const 1))) (subword SF (subword SI newval 1) 0))
+ (set (reg h-fr (add index (const 2))) (subword SF (subword SI newval 2) 0))
+ (set (reg h-fr (add index (const 3))) (subword SF (subword SI newval 3) 0))))
 )
 
 (define-hardware
@@ -89,12 +84,12 @@
   (type register DF (32))
   (indices keyword "%" (.map build-freg-name (.iota 32 0 2)))
   (get (index) (join DF SI
-      (reg h-fr index)
-      (reg h-fr (add index (const 1)))))
+      (subword SI (reg h-fr index) 0)
+      (subword SI (reg h-fr (add index (const 1))) 0)))
   (set (index newval)
        (sequence ()
- (set (reg h-fr index) (subword SI newval 0))
- (set (reg h-fr (add index (const 1))) (subword SI newval 1))))
+ (set (reg h-fr index) (subword SF (subword SI newval 0) 0))
+ (set (reg h-fr (add index (const 1))) (subword SF (subword SI newval 1) 0))))
 )
 
 (define-hardware
@@ -105,16 +100,16 @@
   (type register TF (16))
   (indices keyword "%" (.map build-freg-name (.iota 16 0 4)))
   (get (index) (join TF SI
-      (reg h-fr index)
-      (reg h-fr (add index (const 1)))
-      (reg h-fr (add index (const 2)))
-      (reg h-fr (add index (const 3)))))
+      (subword SI (reg h-fr index) 0)
+      (subword SI (reg h-fr (add index (const 1))) 0)
+      (subword SI (reg h-fr (add index (const 2))) 0)
+      (subword SI (reg h-fr (add index (const 3))) 0)))
   (set (index newval)
        (sequence ()
- (set (reg h-fr index) (subword SI newval 0))
- (set (reg h-fr (add index (const 1))) (subword SI newval 1))
- (set (reg h-fr (add index (const 2))) (subword SI newval 2))
- (set (reg h-fr (add index (const 3))) (subword SI newval 3))))
+ (set (reg h-fr index) (subword SF (subword SI newval 0) 0))
+ (set (reg h-fr (add index (const 1))) (subword SF (subword SI newval 1) 0))
+ (set (reg h-fr (add index (const 2))) (subword SF (subword SI newval 2) 0))
+ (set (reg h-fr (add index (const 3))) (subword SF (subword SI newval 3) 0))))
 )
 
 ; fp condition codes

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Re: [PATCH] [SPARC] Get the sparc32 cpus working with latest cgen.

Jose E. Marchesi

Hi.
   
    Note that I did not compile the generated code yet (still working in the
    sim files) but I made sure that all the subword and join variants used
    in the generated code are properly defined in sim/common/cgen-ops.h, and
    that the change in the register sets mode does not affect the generated
    semantic routines in sem-*.c and the field extraction stuff in
    decode*.c.

I can now confirm that the generated files compile and link properly.

--
Jose E. Marchesi         http://www.jemarch.net
GNU Project              http://www.gnu.org