[PATCH, BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension

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[PATCH, BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension

Sudakshina Das
Hi

This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
Memory Tagging Extension (MTE) is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag setting instructions from
MTE which consists of the following instructions:
- STG [<Xn|SP>, #<simm>]
- STG [<Xn|SP>, #<simm>]!
- STG [<Xn|SP>], #<simm>
- STZG [<Xn|SP>, #<simm>]
- STZG [<Xn|SP>, #<simm>]!
- STZG [<Xn|SP>], #<simm>
- ST2G [<Xn|SP>, #<simm>]
- ST2G [<Xn|SP>, #<simm>]!
- ST2G [<Xn|SP>], #<simm>
- STZ2G [<Xn|SP>, #<simm>]
- STZ2G [<Xn|SP>, #<simm>]!
- STZ2G [<Xn|SP>], #<simm>
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
- STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
- STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>

where
<Xn|SP> : Is the 64-bit GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range -4096 to 4080, defaulting to 0.

Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
Added test.

Is this ok for trunk?

Thanks
Sudi

*** include/ChangeLog ***

2018-xx-xx  Sudakshina Das  <[hidden email]>

        * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
        and AARCH64_OPND_ADDR_SIMM13.
        (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.

*** opcodes/ChangeLog ***

2018-xx-xx  Sudakshina Das  <[hidden email]>

        * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
        for AARCH64_OPND_QLF_imm_tag.
        (operand_general_constraint_met_p): Add case for
        AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
        (aarch64_print_operand): Likewise.
        * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
        (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
        for both offset and pre/post indexed versions.
        (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
        * aarch64-asm-2.c: Regenarated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-xx-xx  Sudakshina Das  <[hidden email]>

        * config/tc-aarch64.c (parse_operands): Add switch case for
        AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
        (fix_insn): Likewise.
        * testsuite/gas/aarch64/armv8_5-a-mte.s: Add tests for stg,
        st2g, stzg, stz2g and stgp.
        * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.


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Re: [PATCH, BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension

Richard Earnshaw (lists)
On 09/10/2018 18:24, Sudakshina Das wrote:

> Hi
>
> This patch is part of the patch series to add support for ARMv8.5-A
> Memory Tagging Extensions.
> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
> Memory Tagging Extension (MTE) is an optional extension to
> ARMv8.5-A and is enabled using the +memtag command line option.
>
> This patch add support to the Tag setting instructions from
> MTE which consists of the following instructions:
> - STG [<Xn|SP>, #<simm>]
> - STG [<Xn|SP>, #<simm>]!
> - STG [<Xn|SP>], #<simm>
> - STZG [<Xn|SP>, #<simm>]
> - STZG [<Xn|SP>, #<simm>]!
> - STZG [<Xn|SP>], #<simm>
> - ST2G [<Xn|SP>, #<simm>]
> - ST2G [<Xn|SP>, #<simm>]!
> - ST2G [<Xn|SP>], #<simm>
> - STZ2G [<Xn|SP>, #<simm>]
> - STZ2G [<Xn|SP>, #<simm>]!
> - STZ2G [<Xn|SP>], #<simm>
> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
> - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
>
> where
> <Xn|SP> : Is the 64-bit GPR or Stack pointer.
> <simm> : Is the optional signed immediate offset, a multiple of 16
> in the range -4096 to 4080, defaulting to 0.
>
> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
> Added test.
>
> Is this ok for trunk?
>
> Thanks
> Sudi
>
> *** include/ChangeLog ***
>
> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>
> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
> and AARCH64_OPND_ADDR_SIMM13.
> (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
>
> *** opcodes/ChangeLog ***
>
> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>
> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
> for AARCH64_OPND_QLF_imm_tag.
> (operand_general_constraint_met_p): Add case for
> AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
> (aarch64_print_operand): Likewise.
> * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
> (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
> for both offset and pre/post indexed versions.
> (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
> * aarch64-asm-2.c: Regenarated.
> * aarch64-dis-2.c: Regenerated.
> * aarch64-opc-2.c: Regenerated.
>
> *** gas/ChangeLog ***
>
> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>
> * config/tc-aarch64.c (parse_operands): Add switch case for
> AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
> (fix_insn): Likewise.
> * testsuite/gas/aarch64/armv8_5-a-mte.s: Add tests for stg,
> st2g, stzg, stz2g and stgp.
> * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>

aarch64-opc.c

Same issues as earlier patch re independent if clauses and mte/memtag.

Otherwise OK.

R.
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Re: [PATCH, BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension

Sudakshina Das
Hi Richard

On 30/10/18 09:53, Richard Earnshaw (lists) wrote:

> On 09/10/2018 18:24, Sudakshina Das wrote:
>> Hi
>>
>> This patch is part of the patch series to add support for ARMv8.5-A
>> Memory Tagging Extensions.
>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>> Memory Tagging Extension (MTE) is an optional extension to
>> ARMv8.5-A and is enabled using the +memtag command line option.
>>
>> This patch add support to the Tag setting instructions from
>> MTE which consists of the following instructions:
>> - STG [<Xn|SP>, #<simm>]
>> - STG [<Xn|SP>, #<simm>]!
>> - STG [<Xn|SP>], #<simm>
>> - STZG [<Xn|SP>, #<simm>]
>> - STZG [<Xn|SP>, #<simm>]!
>> - STZG [<Xn|SP>], #<simm>
>> - ST2G [<Xn|SP>, #<simm>]
>> - ST2G [<Xn|SP>, #<simm>]!
>> - ST2G [<Xn|SP>], #<simm>
>> - STZ2G [<Xn|SP>, #<simm>]
>> - STZ2G [<Xn|SP>, #<simm>]!
>> - STZ2G [<Xn|SP>], #<simm>
>> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
>> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
>> - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
>>
>> where
>> <Xn|SP> : Is the 64-bit GPR or Stack pointer.
>> <simm> : Is the optional signed immediate offset, a multiple of 16
>> in the range -4096 to 4080, defaulting to 0.
>>
>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>> Added test.
>>
>> Is this ok for trunk?
>>
>> Thanks
>> Sudi
>>
>> *** include/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>
>> * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
>> and AARCH64_OPND_ADDR_SIMM13.
>> (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
>>
>> *** opcodes/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>
>> * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
>> for AARCH64_OPND_QLF_imm_tag.
>> (operand_general_constraint_met_p): Add case for
>> AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>> (aarch64_print_operand): Likewise.
>> * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
>> (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
>> for both offset and pre/post indexed versions.
>> (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
>> * aarch64-asm-2.c: Regenarated.
>> * aarch64-dis-2.c: Regenerated.
>> * aarch64-opc-2.c: Regenerated.
>>
>> *** gas/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>
>> * config/tc-aarch64.c (parse_operands): Add switch case for
>> AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>> (fix_insn): Likewise.
>> * testsuite/gas/aarch64/armv8_5-a-mte.s: Add tests for stg,
>> st2g, stzg, stz2g and stgp.
>> * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>>
>
> aarch64-opc.c
>
> Same issues as earlier patch re independent if clauses and mte/memtag.
>
> Otherwise OK.
>
> R.
>
*** include/ChangeLog ***

2018-xx-xx  Sudakshina Das  <[hidden email]>

        * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
        and AARCH64_OPND_ADDR_SIMM13.
        (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.

*** opcodes/ChangeLog ***

2018-xx-xx  Sudakshina Das  <[hidden email]>

        * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
        for AARCH64_OPND_QLF_imm_tag.
        (operand_general_constraint_met_p): Add case for
        AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
        (aarch64_print_operand): Likewise.
        * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
        (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
        for both offset and pre/post indexed versions.
        (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
        * aarch64-asm-2.c: Regenerated.
        * aarch64-dis-2.c: Regenerated.
        * aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-xx-xx  Sudakshina Das  <[hidden email]>

        * config/tc-aarch64.c (parse_operands): Add switch case for
        AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
        (fix_insn): Likewise.
        (warn_unpredictable_ldst): Exempt STGP.
        * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg,
        st2g, stzg, stz2g and stgp.
        * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
        * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
        * testsuite/gas/aarch64/illegal-memtag.l: Likewise.

Thanks
Sudi



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Re: [PATCH, BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension

Sudakshina Das
On 02/11/18 16:09, Sudakshina Das wrote:

> Hi Richard
>
> On 30/10/18 09:53, Richard Earnshaw (lists) wrote:
>> On 09/10/2018 18:24, Sudakshina Das wrote:
>>> Hi
>>>
>>> This patch is part of the patch series to add support for ARMv8.5-A
>>> Memory Tagging Extensions.
>>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>>>
>>> Memory Tagging Extension (MTE) is an optional extension to
>>> ARMv8.5-A and is enabled using the +memtag command line option.
>>>
>>> This patch add support to the Tag setting instructions from
>>> MTE which consists of the following instructions:
>>> - STG [<Xn|SP>, #<simm>]
>>> - STG [<Xn|SP>, #<simm>]!
>>> - STG [<Xn|SP>], #<simm>
>>> - STZG [<Xn|SP>, #<simm>]
>>> - STZG [<Xn|SP>, #<simm>]!
>>> - STZG [<Xn|SP>], #<simm>
>>> - ST2G [<Xn|SP>, #<simm>]
>>> - ST2G [<Xn|SP>, #<simm>]!
>>> - ST2G [<Xn|SP>], #<simm>
>>> - STZ2G [<Xn|SP>, #<simm>]
>>> - STZ2G [<Xn|SP>, #<simm>]!
>>> - STZ2G [<Xn|SP>], #<simm>
>>> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
>>> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
>>> - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
>>>
>>> where
>>> <Xn|SP> : Is the 64-bit GPR or Stack pointer.
>>> <simm> : Is the optional signed immediate offset, a multiple of 16
>>> in the range -4096 to 4080, defaulting to 0.
>>>
>>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>>> Added test.
>>>
>>> Is this ok for trunk?
>>>
>>> Thanks
>>> Sudi
>>>
>>> *** include/ChangeLog ***
>>>
>>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>>
>>>     * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
>>>     and AARCH64_OPND_ADDR_SIMM13.
>>>     (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
>>>
>>> *** opcodes/ChangeLog ***
>>>
>>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>>
>>>     * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
>>>     for AARCH64_OPND_QLF_imm_tag.
>>>     (operand_general_constraint_met_p): Add case for
>>>     AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>>>     (aarch64_print_operand): Likewise.
>>>     * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
>>>     (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
>>>     for both offset and pre/post indexed versions.
>>>     (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
>>>     * aarch64-asm-2.c: Regenarated.
>>>     * aarch64-dis-2.c: Regenerated.
>>>     * aarch64-opc-2.c: Regenerated.
>>>
>>> *** gas/ChangeLog ***
>>>
>>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>>
>>>     * config/tc-aarch64.c (parse_operands): Add switch case for
>>>     AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>>>     (fix_insn): Likewise.
>>>     * testsuite/gas/aarch64/armv8_5-a-mte.s: Add tests for stg,
>>>     st2g, stzg, stz2g and stgp.
>>>     * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>>>
>>
>> aarch64-opc.c
>>
>> Same issues as earlier patch re independent if clauses and mte/memtag.
>>
>> Otherwise OK.
>>
>> R.
>>
> *** include/ChangeLog ***
>
> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>
>      * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
>      and AARCH64_OPND_ADDR_SIMM13.
>      (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
>
> *** opcodes/ChangeLog ***
>
> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>
>      * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
>      for AARCH64_OPND_QLF_imm_tag.
>      (operand_general_constraint_met_p): Add case for
>      AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>      (aarch64_print_operand): Likewise.
>      * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
>      (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
>      for both offset and pre/post indexed versions.
>      (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
>      * aarch64-asm-2.c: Regenerated.
>      * aarch64-dis-2.c: Regenerated.
>      * aarch64-opc-2.c: Regenerated.
>
> *** gas/ChangeLog ***
>
> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>
>      * config/tc-aarch64.c (parse_operands): Add switch case for
>      AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>      (fix_insn): Likewise.
>      (warn_unpredictable_ldst): Exempt STGP.
>      * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg,
>      st2g, stzg, stz2g and stgp.
>      * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
>      * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
>      * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
>
New patch. Changelog still applies.

Sudi

> Thanks
> Sudi
>
>



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Re: [PATCH, BINUTILS, AARCH64, 4/8] Add Tag setting instructions in Memory Tagging Extension

Richard Earnshaw (lists)
On 08/11/2018 10:34, Sudakshina Das wrote:

> On 02/11/18 16:09, Sudakshina Das wrote:
>> Hi Richard
>>
>> On 30/10/18 09:53, Richard Earnshaw (lists) wrote:
>>> On 09/10/2018 18:24, Sudakshina Das wrote:
>>>> Hi
>>>>
>>>> This patch is part of the patch series to add support for ARMv8.5-A
>>>> Memory Tagging Extensions.
>>>> (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
>>>>
>>>> Memory Tagging Extension (MTE) is an optional extension to
>>>> ARMv8.5-A and is enabled using the +memtag command line option.
>>>>
>>>> This patch add support to the Tag setting instructions from
>>>> MTE which consists of the following instructions:
>>>> - STG [<Xn|SP>, #<simm>]
>>>> - STG [<Xn|SP>, #<simm>]!
>>>> - STG [<Xn|SP>], #<simm>
>>>> - STZG [<Xn|SP>, #<simm>]
>>>> - STZG [<Xn|SP>, #<simm>]!
>>>> - STZG [<Xn|SP>], #<simm>
>>>> - ST2G [<Xn|SP>, #<simm>]
>>>> - ST2G [<Xn|SP>, #<simm>]!
>>>> - ST2G [<Xn|SP>], #<simm>
>>>> - STZ2G [<Xn|SP>, #<simm>]
>>>> - STZ2G [<Xn|SP>, #<simm>]!
>>>> - STZ2G [<Xn|SP>], #<simm>
>>>> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]
>>>> - STGP <Xt>, <Xt2>, [<Xn|SP>, #<imm>]!
>>>> - STGP <Xt>, <Xt2>, [<Xn|SP>], #<imm>
>>>>
>>>> where
>>>> <Xn|SP> : Is the 64-bit GPR or Stack pointer.
>>>> <simm> : Is the optional signed immediate offset, a multiple of 16
>>>> in the range -4096 to 4080, defaulting to 0.
>>>>
>>>> Testing done: Builds and reg tests all pass on aarch64-none-linux-gnu.
>>>> Added test.
>>>>
>>>> Is this ok for trunk?
>>>>
>>>> Thanks
>>>> Sudi
>>>>
>>>> *** include/ChangeLog ***
>>>>
>>>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>>>
>>>>     * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
>>>>     and AARCH64_OPND_ADDR_SIMM13.
>>>>     (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
>>>>
>>>> *** opcodes/ChangeLog ***
>>>>
>>>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>>>
>>>>     * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
>>>>     for AARCH64_OPND_QLF_imm_tag.
>>>>     (operand_general_constraint_met_p): Add case for
>>>>     AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>>>>     (aarch64_print_operand): Likewise.
>>>>     * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
>>>>     (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
>>>>     for both offset and pre/post indexed versions.
>>>>     (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
>>>>     * aarch64-asm-2.c: Regenarated.
>>>>     * aarch64-dis-2.c: Regenerated.
>>>>     * aarch64-opc-2.c: Regenerated.
>>>>
>>>> *** gas/ChangeLog ***
>>>>
>>>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>>>
>>>>     * config/tc-aarch64.c (parse_operands): Add switch case for
>>>>     AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>>>>     (fix_insn): Likewise.
>>>>     * testsuite/gas/aarch64/armv8_5-a-mte.s: Add tests for stg,
>>>>     st2g, stzg, stz2g and stgp.
>>>>     * testsuite/gas/aarch64/armv8_5-a-mte.d: Likewise.
>>>>
>>>
>>> aarch64-opc.c
>>>
>>> Same issues as earlier patch re independent if clauses and mte/memtag.
>>>
>>> Otherwise OK.
>>>
>>> R.
>>>
>> *** include/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>
>>      * opcode/aarch64.h (aarch64_opnd): Add AARCH64_OPND_ADDR_SIMM11
>>      and AARCH64_OPND_ADDR_SIMM13.
>>      (aarch64_opnd_qualifier): Add new AARCH64_OPND_QLF_imm_tag.
>>
>> *** opcodes/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>
>>      * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
>>      for AARCH64_OPND_QLF_imm_tag.
>>      (operand_general_constraint_met_p): Add case for
>>      AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>>      (aarch64_print_operand): Likewise.
>>      * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
>>      (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
>>      for both offset and pre/post indexed versions.
>>      (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
>>      * aarch64-asm-2.c: Regenerated.
>>      * aarch64-dis-2.c: Regenerated.
>>      * aarch64-opc-2.c: Regenerated.
>>
>> *** gas/ChangeLog ***
>>
>> 2018-xx-xx  Sudakshina Das  <[hidden email]>
>>
>>      * config/tc-aarch64.c (parse_operands): Add switch case for
>>      AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
>>      (fix_insn): Likewise.
>>      (warn_unpredictable_ldst): Exempt STGP.
>>      * testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for stg,
>>      st2g, stzg, stz2g and stgp.
>>      * testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
>>      * testsuite/gas/aarch64/illegal-memtag.s: Likewise.
>>      * testsuite/gas/aarch64/illegal-memtag.l: Likewise.
>>
> New patch. Changelog still applies.

OK.

R.

>
> Sudi
>
>> Thanks
>> Sudi
>>
>>
>
>
>
> rb10008.patch
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 5f79e92c04ad8fba38cbc4fdf2664bfd63e1b891..a5eee96233d78bbdcedc552597d056cb442fb245 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -6214,6 +6214,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
>  
>   case AARCH64_OPND_ADDR_SIMM9:
>   case AARCH64_OPND_ADDR_SIMM9_2:
> + case AARCH64_OPND_ADDR_SIMM11:
> + case AARCH64_OPND_ADDR_SIMM13:
>    po_misc_or_fail (parse_address (&str, info));
>    if (info->addr.pcrel || info->addr.offset.is_reg
>        || (!info->addr.preind && !info->addr.postind)
> @@ -6773,6 +6775,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>    && (opnds[0].reg.regno == opnds[2].addr.base_regno
>      || opnds[1].reg.regno == opnds[2].addr.base_regno)
>    && opnds[2].addr.base_regno != REG_SP
> +  /* Exempt STGP.  */
> +  && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11)
>    && opnds[2].addr.writeback)
>      as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
>        /* Load operations must load different registers.  */
> @@ -7674,6 +7678,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value)
>      case AARCH64_OPND_ADDR_SIMM9_2:
>      case AARCH64_OPND_ADDR_SIMM10:
>      case AARCH64_OPND_ADDR_UIMM12:
> +    case AARCH64_OPND_ADDR_SIMM11:
> +    case AARCH64_OPND_ADDR_SIMM13:
>        /* Immediate offset in an address.  */
>        insn = get_aarch64_insn (buf);
>  
> diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
> index a7cb6c4a6adcced8d1ec6c56f6f5293f3d4f773d..41406464bb84731e6bc65aa65f008efec6def905 100644
> --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
> +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
> @@ -55,3 +55,61 @@ Disassembly of section \.text:
>  .*: badb037f cmpp x27, x27
>  .*: bac003ff cmpp sp, x0
>  .*: badf001f cmpp x0, sp
> +.*: d920081f stg \[x0\]
> +.*: d9200b7f stg \[x27\]
> +.*: d93fb81f stg \[x0, #-80\]
> +.*: d9200c1f stg \[x0, #0\]!
> +.*: d920ac1f stg \[x0, #160\]!
> +.*: d920041f stg \[x0\], #0
> +.*: d93a641f stg \[x0\], #-1440
> +.*: d92ffbff stg \[sp, #4080\]
> +.*: d9300bff stg \[sp, #-4096\]
> +.*: d92fffff stg \[sp, #4080\]!
> +.*: d93007ff stg \[sp\], #-4096
> +.*: d960081f stzg \[x0\]
> +.*: d9600b7f stzg \[x27\]
> +.*: d97fb81f stzg \[x0, #-80\]
> +.*: d9600c1f stzg \[x0, #0\]!
> +.*: d960ac1f stzg \[x0, #160\]!
> +.*: d960041f stzg \[x0\], #0
> +.*: d97a641f stzg \[x0\], #-1440
> +.*: d96ffbff stzg \[sp, #4080\]
> +.*: d9700bff stzg \[sp, #-4096\]
> +.*: d96fffff stzg \[sp, #4080\]!
> +.*: d97007ff stzg \[sp\], #-4096
> +.*: d9a0081f st2g \[x0\]
> +.*: d9a00b7f st2g \[x27\]
> +.*: d9bfb81f st2g \[x0, #-80\]
> +.*: d9a00c1f st2g \[x0, #0\]!
> +.*: d9a0ac1f st2g \[x0, #160\]!
> +.*: d9a0041f st2g \[x0\], #0
> +.*: d9ba641f st2g \[x0\], #-1440
> +.*: d9affbff st2g \[sp, #4080\]
> +.*: d9b00bff st2g \[sp, #-4096\]
> +.*: d9afffff st2g \[sp, #4080\]!
> +.*: d9b007ff st2g \[sp\], #-4096
> +.*: d9e0081f stz2g \[x0\]
> +.*: d9e00b7f stz2g \[x27\]
> +.*: d9ffb81f stz2g \[x0, #-80\]
> +.*: d9e00c1f stz2g \[x0, #0\]!
> +.*: d9e0ac1f stz2g \[x0, #160\]!
> +.*: d9e0041f stz2g \[x0\], #0
> +.*: d9fa641f stz2g \[x0\], #-1440
> +.*: d9effbff stz2g \[sp, #4080\]
> +.*: d9f00bff stz2g \[sp, #-4096\]
> +.*: d9efffff stz2g \[sp, #4080\]!
> +.*: d9f007ff stz2g \[sp\], #-4096
> +.*: 69000000 stgp x0, x0, \[x0\]
> +.*: 69006c00 stgp x0, x27, \[x0\]
> +.*: 6900001b stgp x27, x0, \[x0\]
> +.*: 69006c1b stgp x27, x27, \[x0\]
> +.*: 69000360 stgp x0, x0, \[x27\]
> +.*: 693d8000 stgp x0, x0, \[x0, #-80\]
> +.*: 69800000 stgp x0, x0, \[x0, #0\]!
> +.*: 69850000 stgp x0, x0, \[x0, #160\]!
> +.*: 68800000 stgp x0, x0, \[x0\], #0
> +.*: 68bb8000 stgp x0, x0, \[x0\], #-144
> +.*: 691f801f stgp xzr, x0, \[x0, #1008\]
> +.*: 69207c00 stgp x0, xzr, \[x0, #-1024\]
> +.*: 699f83e0 stgp x0, x0, \[sp, #1008\]!
> +.*: 68a003e0 stgp x0, x0, \[sp\], #-1024
> diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
> index f17f87efdb4ad92e89739028235b0ba8f5add0d9..729dae6f49eb74c0e11c4ff0ed02f4ab22e5bcdf 100644
> --- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
> +++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
> @@ -16,6 +16,20 @@ func:
>   \op x27, x27, #0, #0
>   .endm
>  
> + .macro expand_stg op
> + \op [x0, #0]
> + \op [x27, #0]
> + \op [x0, #-80]
> + \op [x0, #0]!
> + \op [x0, #160]!
> + \op [x0], #0
> + \op [x0], #-1440
> + \op [sp, #4080]
> + \op [sp, #-4096]
> + \op [sp, #4080]!
> + \op [sp], #-4096
> + .endm
> +
>   # IRG
>   expand_3_reg irg
>   irg sp, x0
> @@ -55,3 +69,23 @@ func:
>   cmpp x27, x27
>   cmpp sp, x0
>   cmpp x0, sp
> +
> + expand_stg stg
> + expand_stg stzg
> + expand_stg st2g
> + expand_stg stz2g
> +
> + stgp x0, x0, [x0, #0]
> + stgp x0, x27, [x0, #0]
> + stgp x27, x0, [x0, #0]
> + stgp x27, x27, [x0, #0]
> + stgp x0, x0, [x27, #0]
> + stgp x0, x0, [x0, #-80]
> + stgp x0, x0, [x0, #0]!
> + stgp x0, x0, [x0, #160]!
> + stgp x0, x0, [x0], #0
> + stgp x0, x0, [x0], #-144
> + stgp xzr, x0, [x0, #1008]
> + stgp x0, xzr, [x0, #-1024]
> + stgp x0, x0, [sp, #1008]!
> + stgp x0, x0, [sp], #-1024
> diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
> index 4da0c3540a353b968dc8a54161881bcc220f0bd6..dd568ccd4eea69d329343cc66ef1d2868968b6c5 100644
> --- a/gas/testsuite/gas/aarch64/illegal-memtag.l
> +++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
> @@ -4,6 +4,12 @@
>  [^:]*:[0-9]+: Error: immediate value out of range 0 to 1008 at operand 3 -- `subg x1,x2,-16,#0x3'
>  [^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `addg x1,x2,#0x3f0,#0x10'
>  [^:]*:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `subg x1,x2,#0x3f0,-4'
> +[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 1 -- `stg \[x1,#15\]'
> +[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `stzg \[x1,#-4097]!'
> +[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `st2g \[x1],#4096'
> +[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
> +[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
> +[^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
>  [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
>  [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
>  [^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
> @@ -20,3 +26,10 @@
>  [^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
>  [^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
>  [^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
> +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stg \[xzr,#0\]'
> +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `st2g \[xzr,#0]!'
> +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stzg \[xzr],#0'
> +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 1 -- `stz2g \[xzr,#0\]'
> +[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
> +[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
> +[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
> diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
> index 7eab07f4d85591df898ed14f0d2ff86327445892..2a66366ebdec78cba3b4d453eaa6681dd78fc1e0 100644
> --- a/gas/testsuite/gas/aarch64/illegal-memtag.s
> +++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
> @@ -8,6 +8,16 @@ func:
>   addg x1, x2, #0x3f0, #0x10
>   subg x1, x2, #0x3f0, -4
>  
> + # STG/STZG/ST2G : Fail imm
> + stg [x1, #15]
> + stzg [x1, #-4097]!
> + st2g [x1], #4096
> +
> + # STGP : Fail imm
> + stgp x1, x2, [x3, #1009]
> + stgp x1, x2, [x3, #33]
> + stgp x1, x2, [x3, #-1025]
> +
>   # Illegal SP/XZR registers
>   irg xzr, x2, x3
>   irg x1, xzr, x3
> @@ -25,3 +35,10 @@ func:
>   subps x1, x2, xzr
>   cmpp xzr, x2
>   cmpp x2, xzr
> + stg [xzr, #0]
> + st2g [xzr, #0]!
> + stzg [xzr], #0
> + stz2g [xzr, #0]
> + stgp sp, x2, [x3]
> + stgp x1, sp, [x3]
> + stgp x0, x0, [xzr]
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index d6e639db9727273e0a6a4e17f54a1f0b99d08b74..c4c573a478944eca1ef0f7bb84dd95d8354a8e78 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -286,7 +286,11 @@ enum aarch64_opnd
>     the mnemonic name for LDUR/STUR instructions
>     wherever there is no ambiguity.  */
>    AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate.  */
> +  AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
> +   16) immediate.  */
>    AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate.  */
> +  AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
> +   16) immediate.  */
>    AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
>    AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
>    AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed.  */
> @@ -467,6 +471,10 @@ enum aarch64_opnd_qualifier
>    AARCH64_OPND_QLF_P_Z,
>    AARCH64_OPND_QLF_P_M,
>  
> +  /* Used in scaled signed immediate that are scaled by a Tag granule
> +     like in stg, st2g, etc.   */
> +  AARCH64_OPND_QLF_imm_tag,
> +
>    /* Constraint on value.  */
>    AARCH64_OPND_QLF_CR, /* CRn, CRm. */
>    AARCH64_OPND_QLF_imm_0_7,
> diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
> index fc7ac88f1a0ef35f21e27cbf248ee8e45643f597..e53b98a67f9dc9e0b4638695b9c03d55234c5025 100644
> --- a/opcodes/aarch64-asm.c
> +++ b/opcodes/aarch64-asm.c
> @@ -690,7 +690,8 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
>    insert_field (FLD_Rn, code, info->addr.base_regno, 0);
>    /* simm (imm9 or imm7) */
>    imm = info->addr.offset.imm;
> -  if (self->fields[0] == FLD_imm7)
> +  if (self->fields[0] == FLD_imm7
> +     || info->qualifier == AARCH64_OPND_QLF_imm_tag)
>      /* scaled immediate in ld/st pair instructions..  */
>      imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
>    insert_field (self->fields[0], code, imm, 0);
> diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
> index b37741a9aae8c383e94c47f210795a7643f93aa3..defb53dfd2566149f11052f713bf048ecc30334d 100644
> --- a/opcodes/aarch64-dis.c
> +++ b/opcodes/aarch64-dis.c
> @@ -1067,7 +1067,8 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
>    /* simm (imm9 or imm7)  */
>    imm = extract_field (self->fields[0], code, 0);
>    info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
> -  if (self->fields[0] == FLD_imm7)
> +  if (self->fields[0] == FLD_imm7
> +      || info->qualifier == AARCH64_OPND_QLF_imm_tag)
>      /* scaled immediate in ld/st pair instructions.  */
>      info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
>    /* qualifier */
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index d73542f2409786e3537458c5c78d3560594335a1..433336f76848db91da1577b740faea3c2c3bcd68 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -721,6 +721,9 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
>    {0, 0, 0, "z", OQK_OPD_VARIANT},
>    {0, 0, 0, "m", OQK_OPD_VARIANT},
>  
> +  /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc).  */
> +  {16, 0, 0, "tag", OQK_OPD_VARIANT},
> +
>    /* Qualifiers constraining the value range.
>       First 3 fields:
>       Lower bound, higher bound, unused.  */
> @@ -1668,6 +1671,36 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
>      }
>    break;
>  
> + case AARCH64_OPND_ADDR_SIMM11:
> +  /* Signed 11 bits immediate offset (multiple of 16).  */
> +  if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
> +    {
> +      set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
> +      return 0;
> +    }
> +
> +  if (!value_aligned_p (opnd->addr.offset.imm, 16))
> +    {
> +      set_unaligned_error (mismatch_detail, idx, 16);
> +      return 0;
> +    }
> +  break;
> +
> + case AARCH64_OPND_ADDR_SIMM13:
> +  /* Signed 13 bits immediate offset (multiple of 16).  */
> +  if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
> +    {
> +      set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
> +      return 0;
> +    }
> +
> +  if (!value_aligned_p (opnd->addr.offset.imm, 16))
> +    {
> +      set_unaligned_error (mismatch_detail, idx, 16);
> +      return 0;
> +    }
> +  break;
> +
>   case AARCH64_OPND_SIMD_ADDR_POST:
>    /* AdvSIMD load/store multiple structures, post-index.  */
>    assert (idx == 1);
> @@ -3559,6 +3592,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
>      case AARCH64_OPND_ADDR_SIMM9:
>      case AARCH64_OPND_ADDR_SIMM9_2:
>      case AARCH64_OPND_ADDR_SIMM10:
> +    case AARCH64_OPND_ADDR_SIMM11:
> +    case AARCH64_OPND_ADDR_SIMM13:
>      case AARCH64_OPND_ADDR_OFFSET:
>      case AARCH64_OPND_SVE_ADDR_RI_S4x16:
>      case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 498315835593add8efcc097948005ce53fb66556..e70d318d934621b6ef0609033d2257ac439d0ca3 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -125,6 +125,12 @@
>    QLF1(X), \
>  }
>  
> +/* e.g. STG [<Xn|SP>, #<imm9>].  */
> +#define QL_LDST_AT \
> +{ \
> +  QLF1(imm_tag), \
> +}
> +
>  /* e.g. RBIT <Wd>, <Wn>.  */
>  #define QL_I2SAME \
>  { \
> @@ -1218,6 +1224,12 @@
>    QLF3(X, X, S_S), \
>  }
>  
> +/* e.g. STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}].  */
> +#define QL_STGP \
> +{ \
> +  QLF3(X, X, imm_tag), \
> +}
> +
>  /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!.  */
>  #define QL_LDST_PAIR_R \
>  { \
> @@ -3218,6 +3230,15 @@ struct aarch64_opcode aarch64_opcode_table[] =
>    CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>    CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
>    CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
> +  /* Load/store Allocation Tag instructions.  */
> +  MEMTAG_INSN ("stg",  0xd920081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
> +  MEMTAG_INSN ("stzg", 0xd960081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
> +  MEMTAG_INSN ("st2g", 0xd9a0081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
> +  MEMTAG_INSN ("stz2g",0xd9e0081f, 0xffe00c1f, ldst_unscaled, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
> +  MEMTAG_INSN ("stg",  0xd920041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
> +  MEMTAG_INSN ("stzg", 0xd960041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
> +  MEMTAG_INSN ("st2g", 0xd9a0041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
> +  MEMTAG_INSN ("stz2g",0xd9e0041f, 0xffe0041f, ldst_imm9, OP1 (ADDR_SIMM13), QL_LDST_AT, 0),
>    /* Load/store register (unsigned immediate).  */
>    CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
>    CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
> @@ -3314,12 +3335,14 @@ struct aarch64_opcode aarch64_opcode_table[] =
>    CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>    CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>    {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
> +  MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
>    /* Load/store register pair (indexed).  */
>    CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
>    CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
>    CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>    CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
>    {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
> +  MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
>    /* Load register (literal).  */
>    CORE_INSN ("ldr",   0x18000000, 0xbf000000, loadlit, OP_LDR_LIT,   OP2 (Rt, ADDR_PCREL19),    QL_R_PCREL, F_GPRSIZE_IN_Q),
>    CORE_INSN ("ldr",   0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT,  OP2 (Ft, ADDR_PCREL19),    QL_FP_PCREL, 0),
> @@ -4628,8 +4651,12 @@ struct aarch64_opcode aarch64_opcode_table[] =
>        "an address with 9-bit negative or unaligned immediate offset") \
>      Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\
>        "an address with 10-bit scaled, signed immediate offset") \
> +    Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\
> +      "an address with 11-bit signed immediate (multiple of 16) offset")\
>      Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
>        "an address with scaled, unsigned immediate offset") \
> +    Y(ADDRESS, addr_simm, "ADDR_SIMM13", 0, F(FLD_imm9,FLD_index),\
> +      "an address with 13-bit signed immediate (multiple of 16) offset")\
>      Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
>        "an address with base register (no offset)") \
>      Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\
>