[PATCH 3/5] RX: gas - Add RXv3 instruction support.

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[PATCH 3/5] RX: gas - Add RXv3 instruction support.

Yoshinori Sato
Instruction manual.
https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0316ej0100-rxv3sm.pdf

        * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
        (rx_bfield): Add prototype.
        (rx_post): Likewise.
        * config/rx-parse.y: Add v3 instructions and Double FPU registers.
        (DSIZE): Define.
        (POST): Define.
        (rx_check_v3): New. check v3 type.
        (rx_check_dfpu): New. check have double support.
        (double_condition_table): New. dcmp<cond> contiditon.
        (check_condition): Multiple condition support.
        (rx_lex): RXv3 instructions support.
        Add parse dcmp<cond> instruction and Double FPU registers.
        (immediate): Disable optimize in dmov #imm case.
        (displacement): Add double displacement in dmov instraction.
        * config/tc-rx.c (rx_use_conventional_section_names):
        Invert default value in rx-*-linux target.
        (cpu_type): Add additional ELF flags.
        (cpu_type_list): Add RXv3.
        (md_parse_option): Refer elf_flags from cpu_type_list.
        (md_show_usage): Add rxv3 and rxv3-dfpu.
        (rx_bytesT): Add post byte.
        (rx_bfield): New. generate bfmov / bfmovz "imm" field.
        (rx_post): New. Set instruction post byte.
        (md_assemble): Add post byte.
        doc/c-rx.texi: Add cpu types.
        * testsuite/gas/rx/Xtod.d: New.
        * testsuite/gas/rx/Xtod.sm: New.
        * testsuite/gas/rx/bfmov.d: New.
        * testsuite/gas/rx/bfmov.sm: New.
        * testsuite/gas/rx/dabs.d: New.
        * testsuite/gas/rx/dabs.sm: New.
        * testsuite/gas/rx/dadd.d: New.
        * testsuite/gas/rx/dadd.sm: New.
        * testsuite/gas/rx/dcmp.d: New.
        * testsuite/gas/rx/dcmp.sm: New.
        * testsuite/gas/rx/ddiv.d: New.
        * testsuite/gas/rx/ddiv.sm: New.
        * testsuite/gas/rx/dmov.d: New.
        * testsuite/gas/rx/dmov.sm: New.
        * testsuite/gas/rx/dmul.d: New.
        * testsuite/gas/rx/dmul.sm: New.
        * testsuite/gas/rx/dneg.d: New.
        * testsuite/gas/rx/dneg.sm: New.
        * testsuite/gas/rx/dpopm.d: New.
        * testsuite/gas/rx/dpopm.sm: New.
        * testsuite/gas/rx/dpushm.d: New.
        * testsuite/gas/rx/dpushm.sm: New.
        * testsuite/gas/rx/dround.d: New.
        * testsuite/gas/rx/dround.sm: New.
        * testsuite/gas/rx/dsqrt.d: New.
        * testsuite/gas/rx/dsqrt.sm: New.
        * testsuite/gas/rx/dsub.d: New.
        * testsuite/gas/rx/dsub.sm: New.
        * testsuite/gas/rx/dtoX.d: New.
        * testsuite/gas/rx/dtoX.sm: New.
        * testsuite/gas/rx/macros.inc: Add double FPU registers.
        * testsuite/gas/rx/mvfdc.d: New.
        * testsuite/gas/rx/mvfdc.sm: New.
        * testsuite/gas/rx/mvfdr.d: New.
        * testsuite/gas/rx/mvfdr.sm: New.
        * testsuite/gas/rx/mvtdc.d: New.
        * testsuite/gas/rx/mvtdc.sm: New.
        * testsuite/gas/rx/rstr.d: New.
        * testsuite/gas/rx/rstr.sm: New.
        * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
        * testsuite/gas/rx/save.d: New.
        * testsuite/gas/rx/save.sm: New.
        * testsuite/gas/rx/xor.d: New.
        * testsuite/gas/rx/xor.sm: Add pattern.
---
 gas/ChangeLog                   |  72 +++++++++
 gas/config/rx-defs.h            |   6 +-
 gas/config/rx-parse.y           | 325 +++++++++++++++++++++++++++++++++++-----
 gas/config/tc-rx.c              |  57 +++++--
 gas/doc/c-rx.texi               |   8 +-
 gas/testsuite/gas/rx/Xtod.d     |  20 +++
 gas/testsuite/gas/rx/Xtod.sm    |   3 +
 gas/testsuite/gas/rx/bfmov.d    |  72 +++++++++
 gas/testsuite/gas/rx/bfmov.sm   |   2 +
 gas/testsuite/gas/rx/dabs.d     |  13 ++
 gas/testsuite/gas/rx/dabs.sm    |   1 +
 gas/testsuite/gas/rx/dadd.d     |  17 +++
 gas/testsuite/gas/rx/dadd.sm    |   1 +
 gas/testsuite/gas/rx/dcmp.d     |  24 +++
 gas/testsuite/gas/rx/dcmp.sm    |   4 +
 gas/testsuite/gas/rx/ddiv.d     |  16 ++
 gas/testsuite/gas/rx/ddiv.sm    |   1 +
 gas/testsuite/gas/rx/dmov.d     |  76 ++++++++++
 gas/testsuite/gas/rx/dmov.sm    |  13 ++
 gas/testsuite/gas/rx/dmul.d     |  16 ++
 gas/testsuite/gas/rx/dmul.sm    |   1 +
 gas/testsuite/gas/rx/dneg.d     |  12 ++
 gas/testsuite/gas/rx/dneg.sm    |   1 +
 gas/testsuite/gas/rx/dpopm.d    |  16 ++
 gas/testsuite/gas/rx/dpopm.sm   |   2 +
 gas/testsuite/gas/rx/dpushm.d   |  16 ++
 gas/testsuite/gas/rx/dpushm.sm  |   2 +
 gas/testsuite/gas/rx/dround.d   |  12 ++
 gas/testsuite/gas/rx/dround.sm  |   1 +
 gas/testsuite/gas/rx/dsqrt.d    |  12 ++
 gas/testsuite/gas/rx/dsqrt.sm   |   1 +
 gas/testsuite/gas/rx/dsub.d     |  16 ++
 gas/testsuite/gas/rx/dsub.sm    |   1 +
 gas/testsuite/gas/rx/dtoX.d     |  20 +++
 gas/testsuite/gas/rx/dtoX.sm    |   3 +
 gas/testsuite/gas/rx/macros.inc |  10 +-
 gas/testsuite/gas/rx/mvfdc.d    |  16 ++
 gas/testsuite/gas/rx/mvfdc.sm   |   1 +
 gas/testsuite/gas/rx/mvfdr.d    |   9 ++
 gas/testsuite/gas/rx/mvfdr.sm   |   1 +
 gas/testsuite/gas/rx/mvtdc.d    |  17 +++
 gas/testsuite/gas/rx/mvtdc.sm   |   1 +
 gas/testsuite/gas/rx/rstr.d     |  12 ++
 gas/testsuite/gas/rx/rstr.sm    |   2 +
 gas/testsuite/gas/rx/rx.exp     |   4 +-
 gas/testsuite/gas/rx/save.d     |  12 ++
 gas/testsuite/gas/rx/save.sm    |   2 +
 gas/testsuite/gas/rx/xor.d      |   8 +
 gas/testsuite/gas/rx/xor.sm     |   2 +
 49 files changed, 903 insertions(+), 57 deletions(-)
 create mode 100644 gas/testsuite/gas/rx/Xtod.d
 create mode 100644 gas/testsuite/gas/rx/Xtod.sm
 create mode 100644 gas/testsuite/gas/rx/bfmov.d
 create mode 100644 gas/testsuite/gas/rx/bfmov.sm
 create mode 100644 gas/testsuite/gas/rx/dabs.d
 create mode 100644 gas/testsuite/gas/rx/dabs.sm
 create mode 100644 gas/testsuite/gas/rx/dadd.d
 create mode 100644 gas/testsuite/gas/rx/dadd.sm
 create mode 100644 gas/testsuite/gas/rx/dcmp.d
 create mode 100644 gas/testsuite/gas/rx/dcmp.sm
 create mode 100644 gas/testsuite/gas/rx/ddiv.d
 create mode 100644 gas/testsuite/gas/rx/ddiv.sm
 create mode 100644 gas/testsuite/gas/rx/dmov.d
 create mode 100644 gas/testsuite/gas/rx/dmov.sm
 create mode 100644 gas/testsuite/gas/rx/dmul.d
 create mode 100644 gas/testsuite/gas/rx/dmul.sm
 create mode 100644 gas/testsuite/gas/rx/dneg.d
 create mode 100644 gas/testsuite/gas/rx/dneg.sm
 create mode 100644 gas/testsuite/gas/rx/dpopm.d
 create mode 100644 gas/testsuite/gas/rx/dpopm.sm
 create mode 100644 gas/testsuite/gas/rx/dpushm.d
 create mode 100644 gas/testsuite/gas/rx/dpushm.sm
 create mode 100644 gas/testsuite/gas/rx/dround.d
 create mode 100644 gas/testsuite/gas/rx/dround.sm
 create mode 100644 gas/testsuite/gas/rx/dsqrt.d
 create mode 100644 gas/testsuite/gas/rx/dsqrt.sm
 create mode 100644 gas/testsuite/gas/rx/dsub.d
 create mode 100644 gas/testsuite/gas/rx/dsub.sm
 create mode 100644 gas/testsuite/gas/rx/dtoX.d
 create mode 100644 gas/testsuite/gas/rx/dtoX.sm
 create mode 100644 gas/testsuite/gas/rx/mvfdc.d
 create mode 100644 gas/testsuite/gas/rx/mvfdc.sm
 create mode 100644 gas/testsuite/gas/rx/mvfdr.d
 create mode 100644 gas/testsuite/gas/rx/mvfdr.sm
 create mode 100644 gas/testsuite/gas/rx/mvtdc.d
 create mode 100644 gas/testsuite/gas/rx/mvtdc.sm
 create mode 100644 gas/testsuite/gas/rx/rstr.d
 create mode 100644 gas/testsuite/gas/rx/rstr.sm
 create mode 100644 gas/testsuite/gas/rx/save.d
 create mode 100644 gas/testsuite/gas/rx/save.sm

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b21680a158..a15906d7b6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,75 @@
+2018-12-25  Yoshinori Sato  <[hidden email]>
+
+ * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
+ (rx_bfield): Add prototype.
+ (rx_post): Likewise.
+ * config/rx-parse.y: Add v3 instructions and Double FPU registers.
+ (DSIZE): Define.
+ (POST): Define.
+ (rx_check_v3): New. check v3 type.
+ (rx_check_dfpu): New. check have double support.
+ (double_condition_table): New. dcmp<cond> contiditon.
+ (check_condition): Multiple condition support.
+ (rx_lex): RXv3 instructions support.
+ Add parse dcmp<cond> instruction and Double FPU registers.
+ (immediate): Disable optimize in dmov #imm case.
+ (displacement): Add double displacement in dmov instraction.
+ * config/tc-rx.c (rx_use_conventional_section_names):
+ Invert default value in rx-*-linux target.
+ (cpu_type): Add additional ELF flags.
+ (cpu_type_list): Add RXv3.
+ (md_parse_option): Refer elf_flags from cpu_type_list.
+ (md_show_usage): Add rxv3 and rxv3-dfpu.
+ (rx_bytesT): Add post byte.
+ (rx_bfield): New. generate bfmov / bfmovz "imm" field.
+ (rx_post): New. Set instruction post byte.
+ (md_assemble): Add post byte.
+ doc/c-rx.texi: Add cpu types.
+ * testsuite/gas/rx/Xtod.d: New.
+ * testsuite/gas/rx/Xtod.sm: New.
+ * testsuite/gas/rx/bfmov.d: New.
+ * testsuite/gas/rx/bfmov.sm: New.
+ * testsuite/gas/rx/dabs.d: New.
+ * testsuite/gas/rx/dabs.sm: New.
+ * testsuite/gas/rx/dadd.d: New.
+ * testsuite/gas/rx/dadd.sm: New.
+ * testsuite/gas/rx/dcmp.d: New.
+ * testsuite/gas/rx/dcmp.sm: New.
+ * testsuite/gas/rx/ddiv.d: New.
+ * testsuite/gas/rx/ddiv.sm: New.
+ * testsuite/gas/rx/dmov.d: New.
+ * testsuite/gas/rx/dmov.sm: New.
+ * testsuite/gas/rx/dmul.d: New.
+ * testsuite/gas/rx/dmul.sm: New.
+ * testsuite/gas/rx/dneg.d: New.
+ * testsuite/gas/rx/dneg.sm: New.
+ * testsuite/gas/rx/dpopm.d: New.
+ * testsuite/gas/rx/dpopm.sm: New.
+ * testsuite/gas/rx/dpushm.d: New.
+ * testsuite/gas/rx/dpushm.sm: New.
+ * testsuite/gas/rx/dround.d: New.
+ * testsuite/gas/rx/dround.sm: New.
+ * testsuite/gas/rx/dsqrt.d: New.
+ * testsuite/gas/rx/dsqrt.sm: New.
+ * testsuite/gas/rx/dsub.d: New.
+ * testsuite/gas/rx/dsub.sm: New.
+ * testsuite/gas/rx/dtoX.d: New.
+ * testsuite/gas/rx/dtoX.sm: New.
+ * testsuite/gas/rx/macros.inc: Add double FPU registers.
+ * testsuite/gas/rx/mvfdc.d: New.
+ * testsuite/gas/rx/mvfdc.sm: New.
+ * testsuite/gas/rx/mvfdr.d: New.
+ * testsuite/gas/rx/mvfdr.sm: New.
+ * testsuite/gas/rx/mvtdc.d: New.
+ * testsuite/gas/rx/mvtdc.sm: New.
+ * testsuite/gas/rx/rstr.d: New.
+ * testsuite/gas/rx/rstr.sm: New.
+ * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
+ * testsuite/gas/rx/save.d: New.
+ * testsuite/gas/rx/save.sm: New.
+ * testsuite/gas/rx/xor.d: New.
+ * testsuite/gas/rx/xor.sm: Add pattern.
+
 2018-12-19  H.J. Lu  <[hidden email]>
 
  PR gas/23997
diff --git a/gas/config/rx-defs.h b/gas/config/rx-defs.h
index ce2683119e..a55b25fbae 100644
--- a/gas/config/rx-defs.h
+++ b/gas/config/rx-defs.h
@@ -39,7 +39,9 @@ enum rx_cpu_types
   RX610,
   RX200,
   RX100,
-  RXV2
+  RXV2,
+  RXV3,
+  RXV3FPU,
 };
 
 extern int rx_pid_register;
@@ -57,6 +59,7 @@ extern void   rx_op (expressionS, int, int);
 extern void   rx_disp3 (expressionS, int);
 extern void   rx_field5s (expressionS);
 extern void   rx_field5s2 (expressionS);
+extern void   rx_bfield (expressionS, expressionS, expressionS);
 extern void   rx_relax (int, int);
 extern void   rx_linkrelax_dsp (int);
 extern void   rx_linkrelax_imm (int);
@@ -64,6 +67,7 @@ extern void   rx_linkrelax_branch (void);
 extern int    rx_parse (void);
 extern int    rx_wrap (void);
 extern void   rx_note_string_insn_use (void);
+extern void   rx_post (char);
 
 extern char * rx_lex_start;
 extern char * rx_lex_end;
diff --git a/gas/config/rx-parse.y b/gas/config/rx-parse.y
index 04c798d978..4f07a55d82 100644
--- a/gas/config/rx-parse.y
+++ b/gas/config/rx-parse.y
@@ -33,6 +33,7 @@ static int rx_lex (void);
 #define BSIZE 0
 #define WSIZE 1
 #define LSIZE 2
+#define DSIZE 3
 
 /*                       .sb    .sw    .l     .uw   */
 static int sizemap[] = { BSIZE, WSIZE, LSIZE, WSIZE };
@@ -90,6 +91,8 @@ static int sizemap[] = { BSIZE, WSIZE, LSIZE, WSIZE };
 #define PC2(v)             rx_op (v, 2, RXREL_PCREL)
 #define PC3(v)             rx_op (v, 3, RXREL_PCREL)
 
+#define POST(v)            rx_post (v)
+
 #define IMM_(v,pos,size)   F (immediate (v, RXREL_SIGNED, pos, size), pos, 2); \
    if (v.X_op != O_constant && v.X_op != O_big) rx_linkrelax_imm (pos)
 #define IMM(v,pos)   IMM_ (v, pos, 32)
@@ -116,6 +119,8 @@ static int         displacement (expressionS, int);
 static void        rtsd_immediate (expressionS);
 static void   rx_range (expressionS, int, int);
 static void        rx_check_v2 (void);
+static void        rx_check_v3 (void);
+static void        rx_check_dfpu (void);
 
 static int    need_flag = 0;
 static int    rx_in_brackets = 0;
@@ -137,36 +142,37 @@ static int    sub_op2;
   expressionS exp;
 }
 
-%type <regno> REG FLAG CREG BCND BMCND SCCND ACC
+%type <regno> REG FLAG CREG BCND BMCND SCCND ACC DREG DREGH DREGL DCREG DCMP
 %type <regno> flag bwl bw memex
 %type <exp> EXPR disp
 
-%token REG FLAG CREG ACC
+%token REG FLAG CREG ACC DREG DREGH DREGL DCREG
 
 %token EXPR UNKNOWN_OPCODE IS_OPCODE
 
-%token DOT_S DOT_B DOT_W DOT_L DOT_A DOT_UB DOT_UW
+%token DOT_S DOT_B DOT_W DOT_L DOT_A DOT_UB DOT_UW DOT_D
 
 %token ABS ADC ADD AND_
-%token BCLR BCND BMCND BNOT BRA BRK BSET BSR BTST
+%token BCLR BCND BFMOV BFMOVZ BMCND BNOT BRA BRK BSET BSR BTST
 %token CLRPSW CMP
-%token DBT DIV DIVU
+%token DABS DADD DBT DCMP DDIV DIV DIVU DMOV DMUL DNEG
+%token   DPOPM DPUSHM DROUND DSQRT DSUB DTOF DTOI DTOU
 %token EDIV EDIVU EMACA EMSBA EMUL EMULA EMULU
-%token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOI FTOU
-%token INT ITOF
+%token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOD FTOI FTOU
+%token INT ITOD ITOF
 %token JMP JSR
 %token MACHI MACLH MACLO MAX MIN MOV MOVCO MOVLI MOVU MSBHI MSBLH MSBLO MUL
-%token   MULHI MULLH MULLO MULU MVFACHI MVFACGU MVFACMI MVFACLO MVFC MVTACGU
-%token     MVTACHI MVTACLO MVTC MVTIPL
+%token   MULHI MULLH MULLO MULU MVFACHI MVFACGU MVFACMI MVFACLO MVFC MVFDC
+%token     MVFDR MVTACGU MVTACHI MVTACLO MVTC MVTDC MVTIPL
 %token NEG NOP NOT
 %token OR
 %token POP POPC POPM PUSH PUSHA PUSHC PUSHM
 %token RACL RACW RDACL RDACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND
-%token   RTE RTFI RTS RTSD
-%token SAT SATR SBB SCCND SCMPU SETPSW SHAR SHLL SHLR SMOVB SMOVF
+%token   RSTR RTE RTFI RTS RTSD
+%token SAT SATR SAVE SBB SCCND SCMPU SETPSW SHAR SHLL SHLR SMOVB SMOVF
 %token   SMOVU SSTR STNZ STOP STZ SUB SUNTIL SWHILE
 %token TST
-%token UTOF
+%token UTOD UTOF
 %token WAIT
 %token XCHG XOR
 
@@ -630,7 +636,7 @@ statement :
  | DIV   { sub_op = 8; } op_dp20_rim
  | DIVU  { sub_op = 9; } op_dp20_rim
  | TST   { sub_op = 12; } op_dp20_rim
- | XOR   { sub_op = 13; } op_dp20_rim
+ | XOR   { sub_op = 13; } op_xor
  | NOT   { sub_op = 14; sub_op2 = 0; } op_dp20_rr
  | STZ   { sub_op = 14; sub_op2 = 0; } op_dp20_ri
  | STNZ  { sub_op = 15; sub_op2 = 1; } op_dp20_ri
@@ -738,17 +744,17 @@ statement :
  | MVFACLO { sub_op = 1; } mvfa_op
  | RACW '#' EXPR
   { id24 (2, 0x18, 0x00);
-    if (rx_uintop ($3, 4) && $3.X_add_number == 1)
+    if (rx_uintop ($3, 4) && exp_val($3) == 1)
       ;
-    else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
+    else if (rx_uintop ($3, 4) && exp_val($3) == 2)
       F (1, 19, 1);
     else
       as_bad (_("RACW expects #1 or #2"));}
  | RACW '#' EXPR ',' ACC
     { rx_check_v2 (); id24 (2, 0x18, 0x00); F ($5, 16, 1);
-    if (rx_uintop ($3, 4) && $3.X_add_number == 1)
+    if (rx_uintop ($3, 4) && exp_val($3) == 1)
       ;
-    else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
+    else if (rx_uintop ($3, 4) && exp_val($3) == 2)
       F (1, 19, 1);
     else
       as_bad (_("RACW expects #1 or #2"));}
@@ -903,6 +909,99 @@ statement :
       as_bad (_("RDACW expects #1 or #2"));}
 
 /* ---------------------------------------------------------------------- */
+ | BFMOV { rx_check_v3(); sub_op = 1; } op_bfield
+ | BFMOVZ { rx_check_v3(); sub_op = 0; } op_bfield
+
+/* ---------------------------------------------------------------------- */
+ | RSTR { rx_check_v3(); sub_op = 1; } op_save_rstr
+ | SAVE { rx_check_v3(); sub_op = 0; } op_save_rstr
+
+/* ---------------------------------------------------------------------- */
+ | DABS { rx_check_dfpu(); sub_op = 0x0c; sub_op2 = 0x01; } double2_op
+ | DNEG { rx_check_dfpu(); sub_op = 0x0c; sub_op2 = 0x02; } double2_op
+ | DROUND { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x0d; } double2_op
+ | DSQRT { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x00; } double2_op
+ | DTOF { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x0c; } double2_op
+ | DTOI { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x08;} double2_op
+ | DTOU { rx_check_dfpu(); sub_op = 0x0d; sub_op2 = 0x09; } double2_op
+ | DADD { rx_check_dfpu(); sub_op = 0x00; } double3_op
+ | DDIV { rx_check_dfpu(); sub_op = 0x05; } double3_op
+ | DMUL { rx_check_dfpu(); sub_op = 0x02; } double3_op
+ | DSUB { rx_check_dfpu(); sub_op = 0x01; } double3_op
+ | DCMP DREG ',' DREG { rx_check_dfpu();
+    B4(0x76, 0x90, 0x08, 0x00); F($1, 24, 4); F($2, 28, 4); F($4, 16, 4); }
+ | DMOV DOT_D REG ',' DREGH
+ { rx_check_dfpu();
+  B4(0xfd, 0x77, 0x80, 0x03); F($3, 20, 4); F($5, 24, 4); }
+ | DMOV DOT_L REG ',' DREGH
+ { rx_check_dfpu();
+  B4(0xfd, 0x77, 0x80, 0x02); F($3, 20, 4); F($5, 24, 4); }
+ | DMOV DOT_L REG ',' DREGL
+ { rx_check_dfpu();
+  B4(0xfd, 0x77, 0x80, 0x00); F($3, 20, 4); F($5, 24, 4); }
+ | DMOV DOT_L DREGH ',' REG
+ { rx_check_dfpu();
+  B4(0xfd, 0x75, 0x80, 0x02); F($3, 24, 4); F($5, 20, 4); }
+ | DMOV DOT_L DREGL ',' REG
+ { rx_check_dfpu();
+  B4(0xfd, 0x75, 0x80, 0x00); F($3, 24, 4); F($5, 20, 4); }
+ | DMOV DOT_D DREG ',' DREG
+ { rx_check_dfpu();
+  B4(0x76, 0x90, 0x0c, 0x00); F($3, 16, 4); F($5, 24, 4); }
+ | DMOV DOT_D DREG ',' '[' REG ']'
+ { rx_check_dfpu();
+  B4(0xfc, 0x78, 0x08, 0x00); F($6, 16, 4); F($3, 24, 4); }
+ | DMOV DOT_D DREG ',' disp '[' REG ']'
+ { rx_check_dfpu();
+  B3(0xfc, 0x78, 0x08); F($7, 16, 4); DSP($5, 14, DSIZE);
+  POST($3 << 4); }
+ | DMOV DOT_D '[' REG ']' ',' DREG
+ { rx_check_dfpu();
+  B4(0xfc, 0xc8, 0x08, 0x00); F($4, 16, 4); F($7, 24, 4); }
+ | DMOV DOT_D disp '[' REG ']' ',' DREG
+ { rx_check_dfpu();
+  B3(0xfc, 0xc8, 0x08); F($5, 16, 4); DSP($3, 14, DSIZE);
+  POST($8 << 4); }
+ | DMOV DOT_D '#' EXPR ',' DREGH
+ { rx_check_dfpu();
+  B3(0xf9, 0x03, 0x03); F($6, 16, 4); IMM($4, -1); }
+ | DMOV DOT_L '#' EXPR ',' DREGH
+ { rx_check_dfpu();
+  B3(0xf9, 0x03, 0x02); F($6, 16, 4); IMM($4, -1); }
+ | DMOV DOT_L '#' EXPR ',' DREGL
+ { rx_check_dfpu();
+  B3(0xf9, 0x03, 0x00); F($6, 16, 4); IMM($4, -1); }
+ | DPOPM DOT_D DREG '-' DREG
+ { rx_check_dfpu();
+  B3(0x75, 0xb8, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
+ | DPOPM DOT_L DCREG '-' DCREG
+ { rx_check_dfpu();
+  B3(0x75, 0xa8, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
+ | DPUSHM DOT_D DREG '-' DREG
+ { rx_check_dfpu();
+  B3(0x75, 0xb0, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
+ | DPUSHM DOT_L DCREG '-' DCREG
+ { rx_check_dfpu();
+  B3(0x75, 0xa0, 0x00); F($3, 16, 4); F($5 - $3, 20, 4); }
+ | MVFDC DCREG ',' REG
+ { rx_check_dfpu();
+  B4(0xfd, 0x75, 0x80, 0x04); F($2, 24, 4); F($4, 20, 4); }
+ | MVFDR
+ { rx_check_dfpu(); B3(0x75, 0x90, 0x1b); }
+ | MVTDC REG ',' DCREG
+ { rx_check_dfpu();
+  B4(0xfd, 0x77, 0x80, 0x04); F($2, 24, 4); F($4, 20, 4); }
+ | FTOD REG ',' DREG
+ { rx_check_dfpu();
+  B4(0xfd, 0x77, 0x80, 0x0a); F($2, 24, 4); F($4, 20, 4); }
+ | ITOD REG ',' DREG
+ { rx_check_dfpu();
+  B4(0xfd, 0x77, 0x80, 0x09); F($2, 24, 4); F($4, 20, 4); }
+ | UTOD REG ',' DREG
+ { rx_check_dfpu();
+  B4(0xfd, 0x77, 0x80, 0x0d); F($2, 24, 4); F($4, 20, 4); }
+
+/* ---------------------------------------------------------------------- */
 
  ;
 
@@ -1048,6 +1147,35 @@ mvfa_op
         as_bad (_("IMM expects #0 to #2"));}
  ;
 
+op_xor
+ : op_dp20_rim
+ | REG ',' REG ',' REG
+  { rx_check_v3(); B3(0xff,0x60,0x00), F ($5, 12, 4), F ($1, 16, 4), F ($3, 20, 4); }
+ ;
+
+op_bfield
+ : { rx_check_v3(); }
+  '#' EXPR ',' '#' EXPR ',' '#' EXPR ',' REG ',' REG
+  { rx_range($3, 0, 31); rx_range($6, 0, 31); rx_range($9, 1, 31);
+    B3(0xfc, 0x5a + (sub_op << 2), 0); F($11, 16, 4); F($13, 20, 4);
+  rx_bfield($3, $6, $9);}
+ ;
+
+op_save_rstr
+ : '#' EXPR
+  { B3(0xfd,0x76,0xe0 + (sub_op << 4)); UO1($2); }
+ | REG
+  { B4(0xfd,0x76,0xc0 + (sub_op << 4), 0x00); F($1, 20, 4); }
+ ;
+
+double2_op
+ : DREG ',' DREG
+ { B4(0x76, 0x90, sub_op, sub_op2); F($1, 16, 4); F($3, 24, 4);}
+
+double3_op
+ : DREG ',' DREG ',' DREG
+ { B4(0x76, 0x90, sub_op, 0x00); F($1, 28, 4); F($3, 16,4); F($5, 24, 4);}
+
 /* ====================================================================== */
 
 disp :      { $$ = zero_expr (); }
@@ -1135,6 +1263,66 @@ token_table[] =
   { "bbpsw", CREG, 24 },
   { "bbpc", CREG, 25 },
 
+  { "dr0", DREG, 0 },
+  { "dr1", DREG, 1 },
+  { "dr2", DREG, 2 },
+  { "dr3", DREG, 3 },
+  { "dr4", DREG, 4 },
+  { "dr5", DREG, 5 },
+  { "dr6", DREG, 6 },
+  { "dr7", DREG, 7 },
+  { "dr8", DREG, 8 },
+  { "dr9", DREG, 9 },
+  { "dr10", DREG, 10 },
+  { "dr11", DREG, 11 },
+  { "dr12", DREG, 12 },
+  { "dr13", DREG, 13 },
+  { "dr14", DREG, 14 },
+  { "dr15", DREG, 15 },
+  
+  { "drh0", DREGH, 0 },
+  { "drh1", DREGH, 1 },
+  { "drh2", DREGH, 2 },
+  { "drh3", DREGH, 3 },
+  { "drh4", DREGH, 4 },
+  { "drh5", DREGH, 5 },
+  { "drh6", DREGH, 6 },
+  { "drh7", DREGH, 7 },
+  { "drh8", DREGH, 8 },
+  { "drh9", DREGH, 9 },
+  { "drh10", DREGH, 10 },
+  { "drh11", DREGH, 11 },
+  { "drh12", DREGH, 12 },
+  { "drh13", DREGH, 13 },
+  { "drh14", DREGH, 14 },
+  { "drh15", DREGH, 15 },
+
+  { "drl0", DREGL, 0 },
+  { "drl1", DREGL, 1 },
+  { "drl2", DREGL, 2 },
+  { "drl3", DREGL, 3 },
+  { "drl4", DREGL, 4 },
+  { "drl5", DREGL, 5 },
+  { "drl6", DREGL, 6 },
+  { "drl7", DREGL, 7 },
+  { "drl8", DREGL, 8 },
+  { "drl9", DREGL, 9 },
+  { "drl10", DREGL, 10 },
+  { "drl11", DREGL, 11 },
+  { "drl12", DREGL, 12 },
+  { "drl13", DREGL, 13 },
+  { "drl14", DREGL, 14 },
+  { "drl15", DREGL, 15 },
+
+  { "DPSW", DCREG, 0 },
+  { "DCMR", DCREG, 1 },
+  { "DCENT", DCREG, 2 },
+  { "DEPC", DCREG, 3 },
+  { "DCR0", DCREG, 0 },
+  { "DCR1", DCREG, 1 },
+  { "DCR2", DCREG, 2 },
+  { "DCR3", DCREG, 3 },
+  
   { ".s", DOT_S, 0 },
   { ".b", DOT_B, 0 },
   { ".w", DOT_W, 0 },
@@ -1142,6 +1330,7 @@ token_table[] =
   { ".a", DOT_A , 0},
   { ".ub", DOT_UB, 0 },
   { ".uw", DOT_UW , 0},
+  { ".d", DOT_D , 0},
 
   { "c", FLAG, 0 },
   { "z", FLAG, 1 },
@@ -1160,6 +1349,8 @@ token_table[] =
   { "and", AND_, IS_OPCODE },
   OPC(BCLR),
   OPC(BCND),
+  OPC(BFMOV),
+  OPC(BFMOVZ),
   OPC(BMCND),
   OPC(BNOT),
   OPC(BRA),
@@ -1169,9 +1360,23 @@ token_table[] =
   OPC(BTST),
   OPC(CLRPSW),
   OPC(CMP),
+  OPC(DABS),
+  OPC(DADD),
   OPC(DBT),
+  OPC(DDIV),
   OPC(DIV),
   OPC(DIVU),
+  OPC(DMOV),
+  OPC(DMUL),
+  OPC(DNEG),
+  OPC(DPOPM),
+  OPC(DPUSHM),
+  OPC(DROUND),
+  OPC(DSQRT),
+  OPC(DSUB),
+  OPC(DTOF),
+  OPC(DTOI),
+  OPC(DTOU),
   OPC(EDIV),
   OPC(EDIVU),
   OPC(EMACA),
@@ -1185,10 +1390,12 @@ token_table[] =
   OPC(FMUL),
   OPC(FREIT),
   OPC(FSQRT),
+  OPC(FTOD),
   OPC(FTOU),
   OPC(FSUB),
   OPC(FTOI),
   OPC(INT),
+  OPC(ITOD),
   OPC(ITOF),
   OPC(JMP),
   OPC(JSR),
@@ -1197,6 +1404,9 @@ token_table[] =
   OPC(MVFACMI),
   OPC(MVFACLO),
   OPC(MVFC),
+  OPC(MVFDC),
+  OPC(MVFDR),
+  OPC(MVTDC),
   OPC(MVTACGU),
   OPC(MVTACHI),
   OPC(MVTACLO),
@@ -1243,12 +1453,14 @@ token_table[] =
   OPC(ROTL),
   OPC(ROTR),
   OPC(ROUND),
+  OPC(RSTR),
   OPC(RTE),
   OPC(RTFI),
   OPC(RTS),
   OPC(RTSD),
   OPC(SAT),
   OPC(SATR),
+  OPC(SAVE),
   OPC(SBB),
   OPC(SCCND),
   OPC(SCMPU),
@@ -1267,6 +1479,7 @@ token_table[] =
   OPC(SUNTIL),
   OPC(SWHILE),
   OPC(TST),
+  OPC(UTOD),
   OPC(UTOF),
   OPC(WAIT),
   OPC(XCHG),
@@ -1289,12 +1502,13 @@ condition_opcode_table[] =
 
 #define NUM_CONDITION_OPCODES (sizeof (condition_opcode_table) / sizeof (condition_opcode_table[0]))
 
-static struct
+struct condition_symbol
 {
   const char * string;
   int    val;
-}
-condition_table[] =
+};
+
+static struct condition_symbol condition_table[] =
 {
   { "z", 0 },
   { "eq", 0 },
@@ -1314,11 +1528,20 @@ condition_table[] =
   { "n", 7 },
   { "lt", 9 },
   { "le", 11 },
-  { "no", 13 }
+  { "no", 13 },
   /* never = 15 */
 };
 
+static struct condition_symbol double_condition_table[] =
+{
+  { "un", 1 },
+  { "eq", 2 },
+  { "lt", 4 },
+  { "le", 6 },
+};
+
 #define NUM_CONDITIONS (sizeof (condition_table) / sizeof (condition_table[0]))
+#define NUM_DOUBLE_CONDITIONS (sizeof (double_condition_table) / sizeof (double_condition_table[0]))
 
 void
 rx_lex_init (char * beginning, char * ending)
@@ -1333,7 +1556,7 @@ rx_lex_init (char * beginning, char * ending)
 }
 
 static int
-check_condition (const char * base)
+check_condition (const char * base, struct condition_symbol *t, unsigned int num)
 {
   char * cp;
   unsigned int i;
@@ -1343,11 +1566,11 @@ check_condition (const char * base)
   if (memcmp (rx_lex_start, base, strlen (base)))
     return 0;
   cp = rx_lex_start + strlen (base);
-  for (i = 0; i < NUM_CONDITIONS; i ++)
+  for (i = 0; i < num; i ++)
     {
-      if (strcasecmp (cp, condition_table[i].string) == 0)
+      if (strcasecmp (cp, t[i].string) == 0)
  {
-  rx_lval.regno = condition_table[i].val;
+  rx_lval.regno = t[i].val;
   return 1;
  }
     }
@@ -1408,14 +1631,25 @@ rx_lex (void)
  }
 
       if (rx_last_token == 0)
- for (ci = 0; ci < NUM_CONDITION_OPCODES; ci ++)
-  if (check_condition (condition_opcode_table[ci].string))
+ {
+  for (ci = 0; ci < NUM_CONDITION_OPCODES; ci ++)
+    if (check_condition (condition_opcode_table[ci].string,
+ condition_table, NUM_CONDITIONS))
+      {
+ *e = save;
+ rx_lex_start = e;
+ rx_last_token = condition_opcode_table[ci].token;
+ return condition_opcode_table[ci].token;
+      }
+  if  (check_condition ("dcmp", double_condition_table,
+ NUM_DOUBLE_CONDITIONS))
     {
       *e = save;
       rx_lex_start = e;
-      rx_last_token = condition_opcode_table[ci].token;
-      return condition_opcode_table[ci].token;
+      rx_last_token = DCMP;
+      return DCMP;
     }
+ }
 
       for (i = 0; i < NUM_TOKENS; i++)
  if (strcasecmp (rx_lex_start, token_table[i].string) == 0
@@ -1446,7 +1680,7 @@ rx_lex (void)
     rx_in_brackets = 0;
 
   if (rx_in_brackets
-      || rx_last_token == REG
+      || rx_last_token == REG || rx_last_token == DREG || rx_last_token == DCREG
       || strchr ("[],#", *rx_lex_start))
     {
       rx_last_token = *rx_lex_start;
@@ -1654,32 +1888,32 @@ immediate (expressionS exp, int type, int pos, int bits)
  rx_error (_("sbb cannot use symbolic immediates"));
     }
 
-  if (rx_intop (exp, 8, bits))
+  if (pos >= 0 && rx_intop (exp, 8, bits))
     {
       rx_op (exp, 1, type);
       return 1;
     }
-  else if (rx_intop (exp, 16, bits))
+  else if (pos >= 0 && rx_intop (exp, 16, bits))
     {
       rx_op (exp, 2, type);
       return 2;
     }
-  else if (rx_uintop (exp, 16) && bits == 16)
+  else if (pos >= 0 && rx_uintop (exp, 16) && bits == 16)
     {
       rx_op (exp, 2, type);
       return 2;
     }
-  else if (rx_intop (exp, 24, bits))
+  else if (pos >= 0 && rx_intop (exp, 24, bits))
     {
       rx_op (exp, 3, type);
       return 3;
     }
-  else if (rx_intop (exp, 32, bits))
+  else if (pos < 0 || rx_intop (exp, 32, bits))
     {
       rx_op (exp, 4, type);
       return 0;
     }
-  else if (type == RXREL_SIGNED)
+  else if (type == RXREL_SIGNED && pos >= 0)
     {
       /* This is a symbolic immediate, we will relax it later.  */
       rx_relax (RX_RELAX_IMM, pos);
@@ -1754,6 +1988,11 @@ displacement (expressionS exp, int msize)
  rx_error (_("long displacement not long-aligned"));
       vshift = 2;
       break;
+    case DSIZE:
+      if (val & 7)
+ rx_error (_("double displacement not double-aligned"));
+      vshift = 3;
+      break;
     default:
       as_bad (_("displacement with unknown size (internal bug?)\n"));
       break;
@@ -1828,3 +2067,17 @@ rx_check_v2 (void)
   if (rx_cpu < RXV2)
     rx_error (_("target CPU type does not support v2 instructions"));
 }
+
+static void
+rx_check_v3 (void)
+{
+  if (rx_cpu < RXV3)
+    rx_error (_("target CPU type does not support v3 instructions"));
+}
+
+static void
+rx_check_dfpu (void)
+{
+  if (rx_cpu != RXV3FPU)
+    rx_error (_("target CPU type does not support double float instructions"));
+}
diff --git a/gas/config/tc-rx.c b/gas/config/tc-rx.c
index 942fd3585e..d42692886b 100644
--- a/gas/config/tc-rx.c
+++ b/gas/config/tc-rx.c
@@ -44,7 +44,11 @@ const char FLT_CHARS[]            = "dD";
 /* ELF flags to set in the output file header.  */
 static int elf_flags = E_FLAG_RX_ABI;
 
+#ifndef TE_LINUX
 bfd_boolean rx_use_conventional_section_names = FALSE;
+#else
+bfd_boolean rx_use_conventional_section_names = TRUE;
+#endif
 static bfd_boolean rx_use_small_data_limit = FALSE;
 
 static bfd_boolean rx_pid_mode = FALSE;
@@ -108,15 +112,18 @@ struct cpu_type
 {
   const char *cpu_name;
   enum rx_cpu_types type;
+  int flag;
 };
 
 struct cpu_type  cpu_type_list[] =
 {
-  {"rx100",RX100},
-  {"rx200",RX200},
-  {"rx600",RX600},
-  {"rx610",RX610},
-  {"rxv2",RXV2}
+  {"rx100", RX100, 0},
+  {"rx200", RX200, 0},
+  {"rx600", RX600, 0},
+  {"rx610", RX610, 0},
+  {"rxv2",  RXV2,  E_FLAG_RX_V2},
+  {"rxv3",  RXV3,  E_FLAG_RX_V3},
+  {"rxv3-dfpu",  RXV3FPU,  E_FLAG_RX_V3},
 };
 
 int
@@ -181,8 +188,7 @@ md_parse_option (int c ATTRIBUTE_UNUSED, const char * arg ATTRIBUTE_UNUSED)
     if (strcasecmp (arg, cpu_type_list[i].cpu_name) == 0)
       {
  rx_cpu = cpu_type_list[i].type;
- if (rx_cpu == RXV2)
-  elf_flags |= E_FLAG_RX_V2;
+ elf_flags |= cpu_type_list[i].flag;
  return 1;
       }
   }
@@ -212,7 +218,7 @@ md_show_usage (FILE * stream)
   fprintf (stream, _("  --mrelax\n"));
   fprintf (stream, _("  --mpid\n"));
   fprintf (stream, _("  --mint-register=<value>\n"));
-  fprintf (stream, _("  --mcpu=<rx100|rx200|rx600|rx610|rxv2>\n"));
+  fprintf (stream, _("  --mcpu=<rx100|rx200|rx600|rx610|rxv2|rxv3|rxv3-dfpu>\n"));
   fprintf (stream, _("  --mno-allow-string-insns"));
 }
 
@@ -723,6 +729,8 @@ typedef struct rx_bytesT
     fixS *       fixP;
   } fixups[2];
   int n_fixups;
+  char post[1];
+  int n_post;
   struct
   {
     char type;
@@ -947,6 +955,24 @@ rx_field5s2 (expressionS exp)
   rx_bytes.base[1] |= (val     ) & 0x0f;
 }
 
+void
+rx_bfield(expressionS s, expressionS d, expressionS w)
+{
+  int slsb = s.X_add_number;
+  int dlsb = d.X_add_number;
+  int width = w.X_add_number;
+  unsigned int imm =
+    (((dlsb + width) & 0x1f) << 10 | (dlsb << 5) |
+     ((dlsb - slsb) & 0x1f));
+  if ((slsb + width) > 32)
+        as_warn (_("Value %d and %d out of range"), slsb, width);
+  if ((dlsb + width) > 32)
+        as_warn (_("Value %d and %d out of range"), dlsb, width);
+  rx_bytes.ops[0] = imm & 0xff;
+  rx_bytes.ops[1] = (imm >> 8);
+  rx_bytes.n_ops = 2;
+}
+
 #define OP(x) rx_bytes.ops[rx_bytes.n_ops++] = (x)
 
 #define F_PRECISION 2
@@ -1008,6 +1034,11 @@ rx_op (expressionS exp, int nbytes, int type)
     }
 }
 
+void rx_post(char byte)
+{
+  rx_bytes.post[rx_bytes.n_post++] = byte;
+}
+
 int
 rx_wrap (void)
 {
@@ -1133,21 +1164,22 @@ md_assemble (char * str)
     0 /* offset */,
     0 /* opcode */);
       frag_then->fr_opcode = bytes;
-      frag_then->fr_fix += rx_bytes.n_base + rx_bytes.n_ops;
-      frag_then->fr_subtype = rx_bytes.n_base + rx_bytes.n_ops;
+      frag_then->fr_fix += rx_bytes.n_base + rx_bytes.n_ops + rx_bytes.n_post;
+      frag_then->fr_subtype = rx_bytes.n_base + rx_bytes.n_ops + rx_bytes.n_post;
     }
   else
     {
-      bytes = frag_more (rx_bytes.n_base + rx_bytes.n_ops);
+      bytes = frag_more (rx_bytes.n_base + rx_bytes.n_ops + rx_bytes.n_post);
       frag_then = frag_now;
       if (fetchalign_bytes)
- fetchalign_bytes->n_ops = rx_bytes.n_base + rx_bytes.n_ops;
+ fetchalign_bytes->n_ops = rx_bytes.n_base + rx_bytes.n_ops + rx_bytes.n_post;
     }
 
   fetchalign_bytes = NULL;
 
   APPEND (base, n_base);
   APPEND (ops, n_ops);
+  APPEND (post, n_post);
 
   if (rx_bytes.link_relax && rx_bytes.n_fixups)
     {
@@ -1196,7 +1228,6 @@ md_assemble (char * str)
       if (frag_then->tc_frag_data)
  frag_then->tc_frag_data->fixups[i].fixP = f;
     }
-
   dwarf2_emit_insn (idx);
 }
 
diff --git a/gas/doc/c-rx.texi b/gas/doc/c-rx.texi
index b20fd09496..27aee6d82f 100644
--- a/gas/doc/c-rx.texi
+++ b/gas/doc/c-rx.texi
@@ -108,10 +108,10 @@ alignments.  This option is the default.
 @cindex @samp{-mcpu=}
 @item -mcpu=@var{name}
 This option tells the assembler the target CPU type.  Currently the
-@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610} and @code{rxv2}
-are recognised as valid cpu names.  Attempting to assemble an instruction
-not supported by the indicated cpu type will result in an error message
-being generated.
+@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610}, @code{rxv2},
+@code{rxv3} and @code{rxv3-dfpu} are recognised as valid cpu names.
+Attempting to assemble an instructionnot supported by the indicated
+cpu type will result in an error message being generated.
 
 @cindex @samp{-mno-allow-string-insns}
 @item -mno-allow-string-insns
diff --git a/gas/testsuite/gas/rx/Xtod.d b/gas/testsuite/gas/rx/Xtod.d
new file mode 100644
index 0000000000..8bf444bc89
--- /dev/null
+++ b/gas/testsuite/gas/rx/Xtod.d
@@ -0,0 +1,20 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: fd 77 80 0a                   ftod r0, dr0
+   4: fd 77 8f 0a                   ftod r15, dr0
+   8: fd 77 80 fa                   ftod r0, dr15
+   c: fd 77 8f fa                   ftod r15, dr15
+  10: fd 77 80 09                   itod r0, dr0
+  14: fd 77 8f 09                   itod r15, dr0
+  18: fd 77 80 f9                   itod r0, dr15
+  1c: fd 77 8f f9                   itod r15, dr15
+  20: fd 77 80 0d                   utod r0, dr0
+  24: fd 77 8f 0d                   utod r15, dr0
+  28: fd 77 80 fd                   utod r0, dr15
+  2c: fd 77 8f fd                   utod r15, dr15
diff --git a/gas/testsuite/gas/rx/Xtod.sm b/gas/testsuite/gas/rx/Xtod.sm
new file mode 100644
index 0000000000..67f82c0add
--- /dev/null
+++ b/gas/testsuite/gas/rx/Xtod.sm
@@ -0,0 +1,3 @@
+ ftod {reg}, {dreg}
+ itod {reg}, {dreg}
+ utod {reg}, {dreg}
diff --git a/gas/testsuite/gas/rx/bfmov.d b/gas/testsuite/gas/rx/bfmov.d
new file mode 100644
index 0000000000..9d61ff8718
--- /dev/null
+++ b/gas/testsuite/gas/rx/bfmov.d
@@ -0,0 +1,72 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: fc 5e 00 00 04                 bfmov #0, #0, #1, r0, r0
+   5: fc 5e 0f 00 04                 bfmov #0, #0, #1, r0, r15
+   a: fc 5e f0 00 04                 bfmov #0, #0, #1, r15, r0
+   f: fc 5e ff 00 04                 bfmov #0, #0, #1, r15, r15
+  14: fc 5e 00 00 3c                 bfmov #0, #0, #15, r0, r0
+  19: fc 5e 0f 00 3c                 bfmov #0, #0, #15, r0, r15
+  1e: fc 5e f0 00 3c                 bfmov #0, #0, #15, r15, r0
+  23: fc 5e ff 00 3c                 bfmov #0, #0, #15, r15, r15
+  28: fc 5e 00 ef 41                 bfmov #0, #15, #1, r0, r0
+  2d: fc 5e 0f ef 41                 bfmov #0, #15, #1, r0, r15
+  32: fc 5e f0 ef 41                 bfmov #0, #15, #1, r15, r0
+  37: fc 5e ff ef 41                 bfmov #0, #15, #1, r15, r15
+  3c: fc 5e 00 ef 79                 bfmov #0, #15, #15, r0, r0
+  41: fc 5e 0f ef 79                 bfmov #0, #15, #15, r0, r15
+  46: fc 5e f0 ef 79                 bfmov #0, #15, #15, r15, r0
+  4b: fc 5e ff ef 79                 bfmov #0, #15, #15, r15, r15
+  50: fc 5e 00 11 04                 bfmov #15, #0, #1, r0, r0
+  55: fc 5e 0f 11 04                 bfmov #15, #0, #1, r0, r15
+  5a: fc 5e f0 11 04                 bfmov #15, #0, #1, r15, r0
+  5f: fc 5e ff 11 04                 bfmov #15, #0, #1, r15, r15
+  64: fc 5e 00 11 3c                 bfmov #15, #0, #15, r0, r0
+  69: fc 5e 0f 11 3c                 bfmov #15, #0, #15, r0, r15
+  6e: fc 5e f0 11 3c                 bfmov #15, #0, #15, r15, r0
+  73: fc 5e ff 11 3c                 bfmov #15, #0, #15, r15, r15
+  78: fc 5e 00 e0 41                 bfmov #15, #15, #1, r0, r0
+  7d: fc 5e 0f e0 41                 bfmov #15, #15, #1, r0, r15
+  82: fc 5e f0 e0 41                 bfmov #15, #15, #1, r15, r0
+  87: fc 5e ff e0 41                 bfmov #15, #15, #1, r15, r15
+  8c: fc 5e 00 e0 79                 bfmov #15, #15, #15, r0, r0
+  91: fc 5e 0f e0 79                 bfmov #15, #15, #15, r0, r15
+  96: fc 5e f0 e0 79                 bfmov #15, #15, #15, r15, r0
+  9b: fc 5e ff e0 79                 bfmov #15, #15, #15, r15, r15
+  a0: fc 5a 00 00 04                 bfmovz #0, #0, #1, r0, r0
+  a5: fc 5a 0f 00 04                 bfmovz #0, #0, #1, r0, r15
+  aa: fc 5a f0 00 04                 bfmovz #0, #0, #1, r15, r0
+  af: fc 5a ff 00 04                 bfmovz #0, #0, #1, r15, r15
+  b4: fc 5a 00 00 3c                 bfmovz #0, #0, #15, r0, r0
+  b9: fc 5a 0f 00 3c                 bfmovz #0, #0, #15, r0, r15
+  be: fc 5a f0 00 3c                 bfmovz #0, #0, #15, r15, r0
+  c3: fc 5a ff 00 3c                 bfmovz #0, #0, #15, r15, r15
+  c8: fc 5a 00 ef 41                 bfmovz #0, #15, #1, r0, r0
+  cd: fc 5a 0f ef 41                 bfmovz #0, #15, #1, r0, r15
+  d2: fc 5a f0 ef 41                 bfmovz #0, #15, #1, r15, r0
+  d7: fc 5a ff ef 41                 bfmovz #0, #15, #1, r15, r15
+  dc: fc 5a 00 ef 79                 bfmovz #0, #15, #15, r0, r0
+  e1: fc 5a 0f ef 79                 bfmovz #0, #15, #15, r0, r15
+  e6: fc 5a f0 ef 79                 bfmovz #0, #15, #15, r15, r0
+  eb: fc 5a ff ef 79                 bfmovz #0, #15, #15, r15, r15
+  f0: fc 5a 00 11 04                 bfmovz #15, #0, #1, r0, r0
+  f5: fc 5a 0f 11 04                 bfmovz #15, #0, #1, r0, r15
+  fa: fc 5a f0 11 04                 bfmovz #15, #0, #1, r15, r0
+  ff: fc 5a ff 11 04                 bfmovz #15, #0, #1, r15, r15
+ 104: fc 5a 00 11 3c                 bfmovz #15, #0, #15, r0, r0
+ 109: fc 5a 0f 11 3c                 bfmovz #15, #0, #15, r0, r15
+ 10e: fc 5a f0 11 3c                 bfmovz #15, #0, #15, r15, r0
+ 113: fc 5a ff 11 3c                 bfmovz #15, #0, #15, r15, r15
+ 118: fc 5a 00 e0 41                 bfmovz #15, #15, #1, r0, r0
+ 11d: fc 5a 0f e0 41                 bfmovz #15, #15, #1, r0, r15
+ 122: fc 5a f0 e0 41                 bfmovz #15, #15, #1, r15, r0
+ 127: fc 5a ff e0 41                 bfmovz #15, #15, #1, r15, r15
+ 12c: fc 5a 00 e0 79                 bfmovz #15, #15, #15, r0, r0
+ 131: fc 5a 0f e0 79                 bfmovz #15, #15, #15, r0, r15
+ 136: fc 5a f0 e0 79                 bfmovz #15, #15, #15, r15, r0
+ 13b: fc 5a ff e0 79                 bfmovz #15, #15, #15, r15, r15
diff --git a/gas/testsuite/gas/rx/bfmov.sm b/gas/testsuite/gas/rx/bfmov.sm
new file mode 100644
index 0000000000..b09a61f1d0
--- /dev/null
+++ b/gas/testsuite/gas/rx/bfmov.sm
@@ -0,0 +1,2 @@
+ bfmov #{0;15}, #{0;15}, #{1;15}, {reg}, {reg}
+ bfmovz #{0;15}, #{0;15}, #{1;15}, {reg}, {reg}
\ No newline at end of file
diff --git a/gas/testsuite/gas/rx/dabs.d b/gas/testsuite/gas/rx/dabs.d
new file mode 100644
index 0000000000..48762d81e3
--- /dev/null
+++ b/gas/testsuite/gas/rx/dabs.d
@@ -0,0 +1,13 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 0c 01                   dabs dr0, dr0
+   4: 76 90 0c f1                   dabs dr0, dr15
+   8: 76 90 fc 01                   dabs dr15, dr0
+   c: 76 90 fc f1                   dabs dr15, dr15
+
diff --git a/gas/testsuite/gas/rx/dabs.sm b/gas/testsuite/gas/rx/dabs.sm
new file mode 100644
index 0000000000..f2d5e438bb
--- /dev/null
+++ b/gas/testsuite/gas/rx/dabs.sm
@@ -0,0 +1 @@
+ dabs {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/dadd.d b/gas/testsuite/gas/rx/dadd.d
new file mode 100644
index 0000000000..8f948fe339
--- /dev/null
+++ b/gas/testsuite/gas/rx/dadd.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 00 00                   dadd dr0, dr0, dr0
+   4: 76 90 00 f0                   dadd dr0, dr0, dr15
+   8: 76 90 f0 00                   dadd dr0, dr15, dr0
+   c: 76 90 f0 f0                   dadd dr0, dr15, dr15
+  10: 76 90 00 0f                   dadd dr15, dr0, dr0
+  14: 76 90 00 ff                   dadd dr15, dr0, dr15
+  18: 76 90 f0 0f                   dadd dr15, dr15, dr0
+  1c: 76 90 f0 ff                   dadd dr15, dr15, dr15
+
diff --git a/gas/testsuite/gas/rx/dadd.sm b/gas/testsuite/gas/rx/dadd.sm
new file mode 100644
index 0000000000..89c517a6f2
--- /dev/null
+++ b/gas/testsuite/gas/rx/dadd.sm
@@ -0,0 +1 @@
+ dadd {dreg}, {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/dcmp.d b/gas/testsuite/gas/rx/dcmp.d
new file mode 100644
index 0000000000..bf7bc06cbd
--- /dev/null
+++ b/gas/testsuite/gas/rx/dcmp.d
@@ -0,0 +1,24 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 08 10                   dcmpun dr0, dr0
+   4: 76 90 f8 10                   dcmpun dr0, dr15
+   8: 76 90 08 1f                   dcmpun dr15, dr0
+   c: 76 90 f8 1f                   dcmpun dr15, dr15
+  10: 76 90 08 20                   dcmpeq dr0, dr0
+  14: 76 90 f8 20                   dcmpeq dr0, dr15
+  18: 76 90 08 2f                   dcmpeq dr15, dr0
+  1c: 76 90 f8 2f                   dcmpeq dr15, dr15
+  20: 76 90 08 40                   dcmplt dr0, dr0
+  24: 76 90 f8 40                   dcmplt dr0, dr15
+  28: 76 90 08 4f                   dcmplt dr15, dr0
+  2c: 76 90 f8 4f                   dcmplt dr15, dr15
+  30: 76 90 08 60                   dcmple dr0, dr0
+  34: 76 90 f8 60                   dcmple dr0, dr15
+  38: 76 90 08 6f                   dcmple dr15, dr0
+  3c: 76 90 f8 6f                   dcmple dr15, dr15
diff --git a/gas/testsuite/gas/rx/dcmp.sm b/gas/testsuite/gas/rx/dcmp.sm
new file mode 100644
index 0000000000..423451bb59
--- /dev/null
+++ b/gas/testsuite/gas/rx/dcmp.sm
@@ -0,0 +1,4 @@
+ dcmpun {dreg}, {dreg}
+ dcmpeq {dreg}, {dreg}
+ dcmplt {dreg}, {dreg}
+ dcmple {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/ddiv.d b/gas/testsuite/gas/rx/ddiv.d
new file mode 100644
index 0000000000..f40dc5b013
--- /dev/null
+++ b/gas/testsuite/gas/rx/ddiv.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 05 00                   ddiv dr0, dr0, dr0
+   4: 76 90 05 f0                   ddiv dr0, dr0, dr15
+   8: 76 90 f5 00                   ddiv dr0, dr15, dr0
+   c: 76 90 f5 f0                   ddiv dr0, dr15, dr15
+  10: 76 90 05 0f                   ddiv dr15, dr0, dr0
+  14: 76 90 05 ff                   ddiv dr15, dr0, dr15
+  18: 76 90 f5 0f                   ddiv dr15, dr15, dr0
+  1c: 76 90 f5 ff                   ddiv dr15, dr15, dr15
diff --git a/gas/testsuite/gas/rx/ddiv.sm b/gas/testsuite/gas/rx/ddiv.sm
new file mode 100644
index 0000000000..b45ccd7e1c
--- /dev/null
+++ b/gas/testsuite/gas/rx/ddiv.sm
@@ -0,0 +1 @@
+ ddiv {dreg}, {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/dmov.d b/gas/testsuite/gas/rx/dmov.d
new file mode 100644
index 0000000000..2e5ecdb419
--- /dev/null
+++ b/gas/testsuite/gas/rx/dmov.d
@@ -0,0 +1,76 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: fd 77 80 03                   dmov\.d r0, drh0
+   4: fd 77 80 f3                   dmov\.d r0, drh15
+   8: fd 77 8f 03                   dmov\.d r15, drh0
+   c: fd 77 8f f3                   dmov\.d r15, drh15
+  10: fd 77 80 02                   dmov\.l r0, drh0
+  14: fd 77 80 f2                   dmov\.l r0, drh15
+  18: fd 77 8f 02                   dmov\.l r15, drh0
+  1c: fd 77 8f f2                   dmov\.l r15, drh15
+  20: fd 77 80 00                   dmov\.l r0, drl0
+  24: fd 77 80 f0                   dmov\.l r0, drl15
+  28: fd 77 8f 00                   dmov\.l r15, drl0
+  2c: fd 77 8f f0                   dmov\.l r15, drl15
+  30: fd 75 80 02                   dmov\.l drh0, r0
+  34: fd 75 8f 02                   dmov\.l drh0, r15
+  38: fd 75 80 f2                   dmov\.l drh15, r0
+  3c: fd 75 8f f2                   dmov\.l drh15, r15
+  40: fd 75 80 00                   dmov\.l drl0, r0
+  44: fd 75 8f 00                   dmov\.l drl0, r15
+  48: fd 75 80 f0                   dmov\.l drl15, r0
+  4c: fd 75 8f f0                   dmov\.l drl15, r15
+  50: 76 90 0c 00                   dmov\.d dr0, dr0
+  54: 76 90 0c f0                   dmov\.d dr0, dr15
+  58: 76 90 fc 00                   dmov\.d dr15, dr0
+  5c: 76 90 fc f0                   dmov\.d dr15, dr15
+  60: fc 78 08 00                   dmov\.d dr0, \[r0\]
+  64: fc 78 f8 00                   dmov\.d dr0, \[r15\]
+  68: fc 78 08 f0                   dmov\.d dr15, \[r0\]
+  6c: fc 78 f8 f0                   dmov\.d dr15, \[r15\]
+  70: fc 78 08 00                   dmov\.d dr0, \[r0\]
+  74: fc 78 f8 00                   dmov\.d dr0, \[r15\]
+  78: fc 7a 08 ff 01 00             dmov\.d dr0, 4088\[r0\]
+  7e: fc 7a f8 ff 01 00             dmov\.d dr0, 4088\[r15\]
+  84: fc 7a 08 fc ff 00             dmov\.d dr0, 524256\[r0\]
+  8a: fc 7a f8 fc ff 00             dmov\.d dr0, 524256\[r15\]
+  90: fc 78 08 f0                   dmov\.d dr15, \[r0\]
+  94: fc 78 f8 f0                   dmov\.d dr15, \[r15\]
+  98: fc 7a 08 ff 01 f0             dmov\.d dr15, 4088\[r0\]
+  9e: fc 7a f8 ff 01 f0             dmov\.d dr15, 4088\[r15\]
+  a4: fc 7a 08 fc ff f0             dmov\.d dr15, 524256\[r0\]
+  aa: fc 7a f8 fc ff f0             dmov\.d dr15, 524256\[r15\]
+  b0: fc c8 08 00                   dmov\.d \[r0\], dr0
+  b4: fc c8 08 f0                   dmov\.d \[r0\], dr15
+  b8: fc c8 f8 00                   dmov\.d \[r15\], dr0
+  bc: fc c8 f8 f0                   dmov\.d \[r15\], dr15
+  c0: fc c8 08 00                   dmov\.d \[r0\], dr0
+  c4: fc c8 08 f0                   dmov\.d \[r0\], dr15
+  c8: fc c8 f8 00                   dmov\.d \[r15\], dr0
+  cc: fc c8 f8 f0                   dmov\.d \[r15\], dr15
+  d0: fc ca 08 ff 01 00             dmov\.d 4088\[r0\], dr0
+  d6: fc ca 08 ff 01 f0             dmov\.d 4088\[r0\], dr15
+  dc: fc ca f8 ff 01 00             dmov\.d 4088\[r15\], dr0
+  e2: fc ca f8 ff 01 f0             dmov\.d 4088\[r15\], dr15
+  e8: fc ca 08 fc ff 00             dmov\.d 524256\[r0\], dr0
+  ee: fc ca 08 fc ff f0             dmov\.d 524256\[r0\], dr15
+  f4: fc ca f8 fc ff 00             dmov\.d 524256\[r15\], dr0
+  fa: fc ca f8 fc ff f0             dmov\.d 524256\[r15\], dr15
+ 100: f9 03 03 00 00 00 80           dmov\.d #0x80000000, drh0
+ 107: f9 03 f3 00 00 00 80           dmov\.d #0x80000000, drh15
+ 10e: f9 03 03 ff ff ff ff           dmov\.d #-1, drh0
+ 115: f9 03 f3 ff ff ff ff           dmov\.d #-1, drh15
+ 11c: f9 03 02 00 00 00 80           dmov\.l #0x80000000, drh0
+ 123: f9 03 f2 00 00 00 80           dmov\.l #0x80000000, drh15
+ 12a: f9 03 02 ff ff ff ff           dmov\.l #-1, drh0
+ 131: f9 03 f2 ff ff ff ff           dmov\.l #-1, drh15
+ 138: f9 03 00 00 00 00 80           dmov\.l #0x80000000, drl0
+ 13f: f9 03 f0 00 00 00 80           dmov\.l #0x80000000, drl15
+ 146: f9 03 00 ff ff ff ff           dmov\.l #-1, drl0
+ 14d: f9 03 f0 ff ff ff ff           dmov\.l #-1, drl15
diff --git a/gas/testsuite/gas/rx/dmov.sm b/gas/testsuite/gas/rx/dmov.sm
new file mode 100644
index 0000000000..84f4301ee8
--- /dev/null
+++ b/gas/testsuite/gas/rx/dmov.sm
@@ -0,0 +1,13 @@
+ dmov.d {reg}, {dregh}
+ dmov.l {reg}, {dregh}
+ dmov.l {reg}, {dregl}
+ dmov.l {dregh}, {reg}
+ dmov.l {dregl}, {reg}
+ dmov.d {dreg}, {dreg}
+ dmov.d {dreg}, [{reg}]
+ dmov.d {dreg}, {dspD}[{reg}]
+ dmov.d [{reg}], {dreg}
+ dmov.d {dspD}[{reg}], {dreg}
+ dmov.d #{imm32}, {dregh}
+ dmov.l #{imm32}, {dregh}
+ dmov.l #{imm32}, {dregl}
diff --git a/gas/testsuite/gas/rx/dmul.d b/gas/testsuite/gas/rx/dmul.d
new file mode 100644
index 0000000000..4247635d70
--- /dev/null
+++ b/gas/testsuite/gas/rx/dmul.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 02 00                   dmul dr0, dr0, dr0
+   4: 76 90 02 f0                   dmul dr0, dr0, dr15
+   8: 76 90 f2 00                   dmul dr0, dr15, dr0
+   c: 76 90 f2 f0                   dmul dr0, dr15, dr15
+  10: 76 90 02 0f                   dmul dr15, dr0, dr0
+  14: 76 90 02 ff                   dmul dr15, dr0, dr15
+  18: 76 90 f2 0f                   dmul dr15, dr15, dr0
+  1c: 76 90 f2 ff                   dmul dr15, dr15, dr15
diff --git a/gas/testsuite/gas/rx/dmul.sm b/gas/testsuite/gas/rx/dmul.sm
new file mode 100644
index 0000000000..5f946da404
--- /dev/null
+++ b/gas/testsuite/gas/rx/dmul.sm
@@ -0,0 +1 @@
+ dmul {dreg}, {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/dneg.d b/gas/testsuite/gas/rx/dneg.d
new file mode 100644
index 0000000000..9511e79799
--- /dev/null
+++ b/gas/testsuite/gas/rx/dneg.d
@@ -0,0 +1,12 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 0c 02                   dneg dr0, dr0
+   4: 76 90 0c f2                   dneg dr0, dr15
+   8: 76 90 fc 02                   dneg dr15, dr0
+   c: 76 90 fc f2                   dneg dr15, dr15
diff --git a/gas/testsuite/gas/rx/dneg.sm b/gas/testsuite/gas/rx/dneg.sm
new file mode 100644
index 0000000000..ed331e6537
--- /dev/null
+++ b/gas/testsuite/gas/rx/dneg.sm
@@ -0,0 +1 @@
+ dneg {dreg},{dreg}
diff --git a/gas/testsuite/gas/rx/dpopm.d b/gas/testsuite/gas/rx/dpopm.d
new file mode 100644
index 0000000000..34e691790e
--- /dev/null
+++ b/gas/testsuite/gas/rx/dpopm.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 75 b8 17                       dpopm.d dr1-dr8
+   3: 75 b8 1d                       dpopm.d dr1-dr14
+   6: 75 b8 71                       dpopm.d dr7-dr8
+   9: 75 b8 77                       dpopm.d dr7-dr14
+   c: 75 a8 03                       dpopm.l dpsw-depc
+   f: 75 a8 02                       dpopm.l dpsw-decnt
+  12: 75 a8 12                       dpopm.l dcmr-depc
+  15: 75 a8 11                       dpopm.l dcmr-decnt
diff --git a/gas/testsuite/gas/rx/dpopm.sm b/gas/testsuite/gas/rx/dpopm.sm
new file mode 100644
index 0000000000..6c779bd04f
--- /dev/null
+++ b/gas/testsuite/gas/rx/dpopm.sm
@@ -0,0 +1,2 @@
+ dpopm.d {dregPlo}-{dregPhi}
+ dpopm.l {dpsw;dcmr}-{depc;dcent}
diff --git a/gas/testsuite/gas/rx/dpushm.d b/gas/testsuite/gas/rx/dpushm.d
new file mode 100644
index 0000000000..d5a51d082c
--- /dev/null
+++ b/gas/testsuite/gas/rx/dpushm.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 75 b0 17                       dpushm.d dr1-dr8
+   3: 75 b0 1d                       dpushm.d dr1-dr14
+   6: 75 b0 71                       dpushm.d dr7-dr8
+   9: 75 b0 77                       dpushm.d dr7-dr14
+   c: 75 a0 03                       dpushm.l dpsw-depc
+   f: 75 a0 02                       dpushm.l dpsw-decnt
+  12: 75 a0 12                       dpushm.l dcmr-depc
+  15: 75 a0 11                       dpushm.l dcmr-decnt
diff --git a/gas/testsuite/gas/rx/dpushm.sm b/gas/testsuite/gas/rx/dpushm.sm
new file mode 100644
index 0000000000..a6093c41be
--- /dev/null
+++ b/gas/testsuite/gas/rx/dpushm.sm
@@ -0,0 +1,2 @@
+ dpushm.d {dregPlo}-{dregPhi}
+ dpushm.l {dpsw;dcmr}-{depc;dcent}
diff --git a/gas/testsuite/gas/rx/dround.d b/gas/testsuite/gas/rx/dround.d
new file mode 100644
index 0000000000..e88d39e2c0
--- /dev/null
+++ b/gas/testsuite/gas/rx/dround.d
@@ -0,0 +1,12 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 0d 0d                   dround dr0, dr0
+   4: 76 90 0d fd                   dround dr0, dr15
+   8: 76 90 fd 0d                   dround dr15, dr0
+   c: 76 90 fd fd                   dround dr15, dr15
diff --git a/gas/testsuite/gas/rx/dround.sm b/gas/testsuite/gas/rx/dround.sm
new file mode 100644
index 0000000000..6faf34d827
--- /dev/null
+++ b/gas/testsuite/gas/rx/dround.sm
@@ -0,0 +1 @@
+ dround {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/dsqrt.d b/gas/testsuite/gas/rx/dsqrt.d
new file mode 100644
index 0000000000..91a769c999
--- /dev/null
+++ b/gas/testsuite/gas/rx/dsqrt.d
@@ -0,0 +1,12 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 0d 00                   dsqrt dr0, dr0
+   4: 76 90 0d f0                   dsqrt dr0, dr15
+   8: 76 90 fd 00                   dsqrt dr15, dr0
+   c: 76 90 fd f0                   dsqrt dr15, dr15
diff --git a/gas/testsuite/gas/rx/dsqrt.sm b/gas/testsuite/gas/rx/dsqrt.sm
new file mode 100644
index 0000000000..1475b1f8aa
--- /dev/null
+++ b/gas/testsuite/gas/rx/dsqrt.sm
@@ -0,0 +1 @@
+ dsqrt {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/dsub.d b/gas/testsuite/gas/rx/dsub.d
new file mode 100644
index 0000000000..939850e19f
--- /dev/null
+++ b/gas/testsuite/gas/rx/dsub.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 01 00                   dsub dr0, dr0, dr0
+   4: 76 90 01 f0                   dsub dr0, dr0, dr15
+   8: 76 90 f1 00                   dsub dr0, dr15, dr0
+   c: 76 90 f1 f0                   dsub dr0, dr15, dr15
+  10: 76 90 01 0f                   dsub dr15, dr0, dr0
+  14: 76 90 01 ff                   dsub dr15, dr0, dr15
+  18: 76 90 f1 0f                   dsub dr15, dr15, dr0
+  1c: 76 90 f1 ff                   dsub dr15, dr15, dr15
diff --git a/gas/testsuite/gas/rx/dsub.sm b/gas/testsuite/gas/rx/dsub.sm
new file mode 100644
index 0000000000..b0619957d1
--- /dev/null
+++ b/gas/testsuite/gas/rx/dsub.sm
@@ -0,0 +1 @@
+ dsub {dreg}, {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/dtoX.d b/gas/testsuite/gas/rx/dtoX.d
new file mode 100644
index 0000000000..8d7c5eae26
--- /dev/null
+++ b/gas/testsuite/gas/rx/dtoX.d
@@ -0,0 +1,20 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 76 90 0d 0c                   dtof dr0, dr0
+   4: 76 90 0d fc                   dtof dr0, dr15
+   8: 76 90 fd 0c                   dtof dr15, dr0
+   c: 76 90 fd fc                   dtof dr15, dr15
+  10: 76 90 0d 08                   dtoi dr0, dr0
+  14: 76 90 0d f8                   dtoi dr0, dr15
+  18: 76 90 fd 08                   dtoi dr15, dr0
+  1c: 76 90 fd f8                   dtoi dr15, dr15
+  20: 76 90 0d 09                   dtou dr0, dr0
+  24: 76 90 0d f9                   dtou dr0, dr15
+  28: 76 90 fd 09                   dtou dr15, dr0
+  2c: 76 90 fd f9                   dtou dr15, dr15
diff --git a/gas/testsuite/gas/rx/dtoX.sm b/gas/testsuite/gas/rx/dtoX.sm
new file mode 100644
index 0000000000..6faf4970d1
--- /dev/null
+++ b/gas/testsuite/gas/rx/dtoX.sm
@@ -0,0 +1,3 @@
+ dtof {dreg}, {dreg}
+ dtoi {dreg}, {dreg}
+ dtou {dreg}, {dreg}
diff --git a/gas/testsuite/gas/rx/macros.inc b/gas/testsuite/gas/rx/macros.inc
index 02d2fac755..7fc4c42f58 100644
--- a/gas/testsuite/gas/rx/macros.inc
+++ b/gas/testsuite/gas/rx/macros.inc
@@ -6,6 +6,12 @@ macro regPlo {r1;r7}
 macro regPhi {r8;r14}
 macro creg {psw;fpsw;usp;isp;intb;bpsw;bpc;fintv;extb}
 macro pswf {U;I;O;S;Z;C}
+macro dreg {dr0;dr15}
+macro dregh {drh0;drh15}
+macro dregl {drl0;drl15}
+macro dcreg {dpsw;dcmr;dcent;depc}
+macro dregPlo {dr1;dr7}
+macro dregPhi {dr8;dr14}
 
 macro simm8 {-128;127}
 macro simm16 {-32768;32768}
@@ -30,9 +36,11 @@ macro dsp8 252
 macro dsp16 65532
 macro dsp8L 1020
 macro dsp16L 262140
-
+macro dsp8D 4088
+macro dsp16D 524256
 macro dsp {;{dsp8};{dsp16}}
 macro dspL {;{dsp8L};{dsp16L}}
+macro dspD {;{dsp8D};{dsp16D}}
 
 macro memex {.ub;.b;.uw;.w;.l}
 macro memx {dsp}[{reg}]{memex}
diff --git a/gas/testsuite/gas/rx/mvfdc.d b/gas/testsuite/gas/rx/mvfdc.d
new file mode 100644
index 0000000000..c36617a97d
--- /dev/null
+++ b/gas/testsuite/gas/rx/mvfdc.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: fd 75 80 04                   mvfdc dpsw, r0
+   4: fd 75 8f 04                   mvfdc dpsw, r15
+   8: fd 75 80 14                   mvfdc dcmr, r0
+   c: fd 75 8f 14                   mvfdc dcmr, r15
+  10: fd 75 80 24                   mvfdc decnt, r0
+  14: fd 75 8f 24                   mvfdc decnt, r15
+  18: fd 75 80 34                   mvfdc depc, r0
+  1c: fd 75 8f 34                   mvfdc depc, r15
diff --git a/gas/testsuite/gas/rx/mvfdc.sm b/gas/testsuite/gas/rx/mvfdc.sm
new file mode 100644
index 0000000000..8aa9fe386e
--- /dev/null
+++ b/gas/testsuite/gas/rx/mvfdc.sm
@@ -0,0 +1 @@
+ mvfdc {dcreg}, {reg}
\ No newline at end of file
diff --git a/gas/testsuite/gas/rx/mvfdr.d b/gas/testsuite/gas/rx/mvfdr.d
new file mode 100644
index 0000000000..52190a5728
--- /dev/null
+++ b/gas/testsuite/gas/rx/mvfdr.d
@@ -0,0 +1,9 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: 75 90 1b                       mvfdr
diff --git a/gas/testsuite/gas/rx/mvfdr.sm b/gas/testsuite/gas/rx/mvfdr.sm
new file mode 100644
index 0000000000..e5600ae52d
--- /dev/null
+++ b/gas/testsuite/gas/rx/mvfdr.sm
@@ -0,0 +1 @@
+ mvfdr
diff --git a/gas/testsuite/gas/rx/mvtdc.d b/gas/testsuite/gas/rx/mvtdc.d
new file mode 100644
index 0000000000..2b61156910
--- /dev/null
+++ b/gas/testsuite/gas/rx/mvtdc.d
@@ -0,0 +1,17 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: fd 77 80 04                   mvtdc r0, dpsw
+   4: fd 77 81 04                   mvtdc r0, dcmr
+   8: fd 77 82 04                   mvtdc r0, decnt
+   c: fd 77 83 04                   mvtdc r0, depc
+  10: fd 77 80 f4                   mvtdc r15, dpsw
+  14: fd 77 81 f4                   mvtdc r15, dcmr
+  18: fd 77 82 f4                   mvtdc r15, decnt
+  1c: fd 77 83 f4                   mvtdc r15, depc
+
diff --git a/gas/testsuite/gas/rx/mvtdc.sm b/gas/testsuite/gas/rx/mvtdc.sm
new file mode 100644
index 0000000000..4b8f41c243
--- /dev/null
+++ b/gas/testsuite/gas/rx/mvtdc.sm
@@ -0,0 +1 @@
+ mvtdc {reg}, {dcreg}
diff --git a/gas/testsuite/gas/rx/rstr.d b/gas/testsuite/gas/rx/rstr.d
new file mode 100644
index 0000000000..e72aef786b
--- /dev/null
+++ b/gas/testsuite/gas/rx/rstr.d
@@ -0,0 +1,12 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: fd 76 d0 00                   rstr r0
+   4: fd 76 df 00                   rstr r15
+   8: fd 76 f0 00                   rstr #0
+   c: fd 76 f0 ff                   rstr #255
diff --git a/gas/testsuite/gas/rx/rstr.sm b/gas/testsuite/gas/rx/rstr.sm
new file mode 100644
index 0000000000..8075fc5b14
--- /dev/null
+++ b/gas/testsuite/gas/rx/rstr.sm
@@ -0,0 +1,2 @@
+ rstr {reg}
+ rstr #{uimm8}
diff --git a/gas/testsuite/gas/rx/rx.exp b/gas/testsuite/gas/rx/rx.exp
index e6d21dda89..05b4b5042b 100644
--- a/gas/testsuite/gas/rx/rx.exp
+++ b/gas/testsuite/gas/rx/rx.exp
@@ -22,14 +22,14 @@ if { ! [istarget rx-*-*] } {
 }
 
 global ASFLAGS
-set ASFLAGS "--mcpu=rxv2"
+set ASFLAGS "--mcpu=rxv3-dfpu"
 
 foreach test [lsort [glob $srcdir/$subdir/*.sm]] {
     regexp ".*/(.*)\.sm" $test rxjunk rxbase
     exec "$srcdir/$subdir/explode" "-I" "$srcdir/$subdir" "$test" "$srcdir/$subdir/$rxbase.s"
     run_dump_test "$rxbase"
     # Commment out the next line if you want to retain the generated assembler source files.
-    remote_file host delete "$srcdir/$subdir/$rxbase.s"
+#    remote_file host delete "$srcdir/$subdir/$rxbase.s"
 }
 
 run_dump_test "rx-asm-good"
diff --git a/gas/testsuite/gas/rx/save.d b/gas/testsuite/gas/rx/save.d
new file mode 100644
index 0000000000..16a637c517
--- /dev/null
+++ b/gas/testsuite/gas/rx/save.d
@@ -0,0 +1,12 @@
+#objdump: -dr
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+00000000 <.*>:
+   0: fd 76 c0 00                   save r0
+   4: fd 76 cf 00                   save r15
+   8: fd 76 e0 00                   save #0
+   c: fd 76 e0 ff                   save #255
diff --git a/gas/testsuite/gas/rx/save.sm b/gas/testsuite/gas/rx/save.sm
new file mode 100644
index 0000000000..cbf169c6b4
--- /dev/null
+++ b/gas/testsuite/gas/rx/save.sm
@@ -0,0 +1,2 @@
+ save {reg}
+ save #{uimm8}
diff --git a/gas/testsuite/gas/rx/xor.d b/gas/testsuite/gas/rx/xor.d
index cd60251ccf..11b134ef84 100644
--- a/gas/testsuite/gas/rx/xor.d
+++ b/gas/testsuite/gas/rx/xor.d
@@ -86,3 +86,11 @@ Disassembly of section \.text:
  174: 06 62 0d ff fe 7f             xor 65532\[r15\]\.w, r15
  17a: 06 a2 0d f0 ff 3f             xor 65532\[r15\]\.l, r0
  180: 06 a2 0d ff ff 3f             xor 65532\[r15\]\.l, r15
+ 186: ff 60 00                       xor r0, r0, r0
+ 189: ff 6f 00                       xor r0, r0, r15
+ 18c: ff 60 0f                       xor r0, r15, r0
+ 18f: ff 6f 0f                       xor r0, r15, r15
+ 192: ff 60 f0                       xor r15, r0, r0
+ 195: ff 6f f0                       xor r15, r0, r15
+ 198: ff 60 ff                       xor r15, r15, r0
+ 19b: ff 6f ff                       xor r15, r15, r15
diff --git a/gas/testsuite/gas/rx/xor.sm b/gas/testsuite/gas/rx/xor.sm
index 591d352efa..42e94dca5f 100644
--- a/gas/testsuite/gas/rx/xor.sm
+++ b/gas/testsuite/gas/rx/xor.sm
@@ -2,3 +2,5 @@
 
  xor {reg},{reg}
  xor {memx},{reg}
+
+ xor {reg},{reg},{reg}
--
2.11.0

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Re: [PATCH 3/5] RX: gas - Add RXv3 instruction support.

Nick Clifton
Hi Yoshinori,

> * config/rx-defs.h (rx_cpu_types): Add type RXV3 and RXV3FPU.
> (rx_bfield): Add prototype.
> (rx_post): Likewise.
> * config/rx-parse.y: Add v3 instructions and Double FPU registers.
> (DSIZE): Define.
> (POST): Define.
> (rx_check_v3): New. check v3 type.
> (rx_check_dfpu): New. check have double support.
> (double_condition_table): New. dcmp<cond> contiditon.
> (check_condition): Multiple condition support.
> (rx_lex): RXv3 instructions support.
> Add parse dcmp<cond> instruction and Double FPU registers.
> (immediate): Disable optimize in dmov #imm case.
> (displacement): Add double displacement in dmov instraction.
> * config/tc-rx.c (rx_use_conventional_section_names):
> Invert default value in rx-*-linux target.
> (cpu_type): Add additional ELF flags.
> (cpu_type_list): Add RXv3.
> (md_parse_option): Refer elf_flags from cpu_type_list.
> (md_show_usage): Add rxv3 and rxv3-dfpu.
> (rx_bytesT): Add post byte.
> (rx_bfield): New. generate bfmov / bfmovz "imm" field.
> (rx_post): New. Set instruction post byte.
> (md_assemble): Add post byte.
> doc/c-rx.texi: Add cpu types.
> * testsuite/gas/rx/Xtod.d: New.
> * testsuite/gas/rx/Xtod.sm: New.
> * testsuite/gas/rx/bfmov.d: New.
> * testsuite/gas/rx/bfmov.sm: New.
> * testsuite/gas/rx/dabs.d: New.
> * testsuite/gas/rx/dabs.sm: New.
> * testsuite/gas/rx/dadd.d: New.
> * testsuite/gas/rx/dadd.sm: New.
> * testsuite/gas/rx/dcmp.d: New.
> * testsuite/gas/rx/dcmp.sm: New.
> * testsuite/gas/rx/ddiv.d: New.
> * testsuite/gas/rx/ddiv.sm: New.
> * testsuite/gas/rx/dmov.d: New.
> * testsuite/gas/rx/dmov.sm: New.
> * testsuite/gas/rx/dmul.d: New.
> * testsuite/gas/rx/dmul.sm: New.
> * testsuite/gas/rx/dneg.d: New.
> * testsuite/gas/rx/dneg.sm: New.
> * testsuite/gas/rx/dpopm.d: New.
> * testsuite/gas/rx/dpopm.sm: New.
> * testsuite/gas/rx/dpushm.d: New.
> * testsuite/gas/rx/dpushm.sm: New.
> * testsuite/gas/rx/dround.d: New.
> * testsuite/gas/rx/dround.sm: New.
> * testsuite/gas/rx/dsqrt.d: New.
> * testsuite/gas/rx/dsqrt.sm: New.
> * testsuite/gas/rx/dsub.d: New.
> * testsuite/gas/rx/dsub.sm: New.
> * testsuite/gas/rx/dtoX.d: New.
> * testsuite/gas/rx/dtoX.sm: New.
> * testsuite/gas/rx/macros.inc: Add double FPU registers.
> * testsuite/gas/rx/mvfdc.d: New.
> * testsuite/gas/rx/mvfdc.sm: New.
> * testsuite/gas/rx/mvfdr.d: New.
> * testsuite/gas/rx/mvfdr.sm: New.
> * testsuite/gas/rx/mvtdc.d: New.
> * testsuite/gas/rx/mvtdc.sm: New.
> * testsuite/gas/rx/rstr.d: New.
> * testsuite/gas/rx/rstr.sm: New.
> * testsuite/gas/rx/rx.exp: Use rxv3-dfpu option.
> * testsuite/gas/rx/save.d: New.
> * testsuite/gas/rx/save.sm: New.
> * testsuite/gas/rx/xor.d: New.
> * testsuite/gas/rx/xor.sm: Add pattern.
 
Approved - please apply.

Cheers
  Nick