[PATCH 0/3] x86: follow-on to ac0ab1842d

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[PATCH 0/3] x86: follow-on to ac0ab1842d

Jan Beulich-2
1: consistently convert to byte registers for TEST w/ imm optimization
2: assert sane internal state for REX conversions
3: refine when to trigger optimizations

Jan
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[PATCH 1/3] x86: consistently convert to byte registers for TEST w/ imm optimization

Jan Beulich-2
Commit ac0ab1842d ("i386: Also check R12-R15 registers when optimizing
testq to testb") didn't go quite far enough: In order to avoid confusing
other code registers would better be converted to byte ones uniformly.

gas/
2019-12-XX  Jan Beulich  <[hidden email]>

        * config/tc-i386.c (optimize_encoding): Generalize register
        transformation for TEST optimization.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3932,17 +3932,16 @@ optimize_encoding (void)
   i.types[1].bitfield.byte = 1;
   /* Ignore the suffix.  */
   i.suffix = 0;
-  if (base_regnum >= 4)
-    {
-      /* Handle SP, BP, SI, DI and R12-R15 registers.  */
-      if (i.types[1].bitfield.word)
- j = 16;
-      else if (i.types[1].bitfield.dword)
- j = 32;
-      else
- j = 48;
-      i.op[1].regs -= j;
-    }
+  /* Convert to byte registers.  */
+  if (i.types[1].bitfield.word)
+    j = 16;
+  else if (i.types[1].bitfield.dword)
+    j = 32;
+  else
+    j = 48;
+  if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4)
+    j += 8;
+  i.op[1].regs -= j;
  }
     }
   else if (flag_code == CODE_64BIT

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[PATCH 2/3] x86-64: assert sane internal state for REX conversions

Jan Beulich-2
In reply to this post by Jan Beulich-2
For the comments about "hi" registers to be really applicable, RegRex
may not be set on the respective registers. Assert this is the case.

gas/
2019-12-XX  Jan Beulich  <[hidden email]>

        * config/tc-i386.c (md_assemble): Check RegRex is clear during
        REX transformations. Correct comment indentation.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4497,6 +4497,7 @@ md_assemble (char *line)
   if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte
       && (i.op[x].regs->reg_flags & RegRex64) == 0)
     {
+      gas_assert (!(i.op[x].regs->reg_flags & RegRex));
       /* In case it is "hi" register, give up.  */
       if (i.op[x].regs->reg_num > 3)
  as_bad (_("can't encode register '%s%s' in an "
@@ -4515,7 +4516,7 @@ md_assemble (char *line)
   if (i.rex == 0 && i.rex_encoding)
     {
       /* Check if we can add a REX_OPCODE byte.  Look for 8 bit operand
-         that uses legacy register.  If it is "hi" register, don't add
+ that uses legacy register.  If it is "hi" register, don't add
  the REX_OPCODE byte.  */
       int x;
       for (x = 0; x < 2; x++)
@@ -4524,6 +4525,7 @@ md_assemble (char *line)
     && (i.op[x].regs->reg_flags & RegRex64) == 0
     && i.op[x].regs->reg_num > 3)
   {
+    gas_assert (!(i.op[x].regs->reg_flags & RegRex));
     i.rex_encoding = FALSE;
     break;
   }

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[PATCH 3/3] x86: refine when to trigger optimizations

Jan Beulich-2
In reply to this post by Jan Beulich-2
Checking just the base opcode without also checking this isn't a VEX
encoding, and without there being other insn properties avoiding a match
once respective VEX/XOP/EXEX-encoded insns would appear, add respective
checks. At the same time there's no real need to check the extension
opcode to be None for the 0xA8 form - there's nothing it can be confused
with, and non-VEX-and-alike forms also won't appear.

gas/
2019-12-XX  Jan Beulich  <[hidden email]>

        * config/tc-i386.c (optimize_encoding): Add
        is_any_vex_encoding() invocations. Drop respective
        i.tm.extension_opcode == None checks.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3913,13 +3913,13 @@ optimize_encoding (void)
   unsigned int j;
 
   if (optimize_for_space
+      && !is_any_vex_encoding (&i.tm)
       && i.reg_operands == 1
       && i.imm_operands == 1
       && !i.types[1].bitfield.byte
       && i.op[0].imms->X_op == O_constant
       && fits_in_imm7 (i.op[0].imms->X_add_number)
-      && ((i.tm.base_opcode == 0xa8
-   && i.tm.extension_opcode == None)
+      && (i.tm.base_opcode == 0xa8
   || (i.tm.base_opcode == 0xf6
       && i.tm.extension_opcode == 0x0)))
     {
@@ -3945,6 +3945,7 @@ optimize_encoding (void)
  }
     }
   else if (flag_code == CODE_64BIT
+   && !is_any_vex_encoding (&i.tm)
    && ((i.types[1].bitfield.qword
  && i.reg_operands == 1
  && i.imm_operands == 1
@@ -3953,9 +3954,8 @@ optimize_encoding (void)
      && i.tm.extension_opcode == None
      && fits_in_unsigned_long (i.op[0].imms->X_add_number))
     || (fits_in_imm31 (i.op[0].imms->X_add_number)
- && (((i.tm.base_opcode == 0x24
-      || i.tm.base_opcode == 0xa8)
-     && i.tm.extension_opcode == None)
+ && ((i.tm.base_opcode == 0x24
+     || i.tm.base_opcode == 0xa8)
     || (i.tm.base_opcode == 0x80
  && i.tm.extension_opcode == 0x4)
     || ((i.tm.base_opcode == 0xf6
@@ -3967,13 +3967,11 @@ optimize_encoding (void)
        || (i.types[0].bitfield.qword
    && ((i.reg_operands == 2
  && i.op[0].regs == i.op[1].regs
- && ((i.tm.base_opcode == 0x30
-     || i.tm.base_opcode == 0x28)
-    && i.tm.extension_opcode == None))
+ && (i.tm.base_opcode == 0x30
+    || i.tm.base_opcode == 0x28))
        || (i.reg_operands == 1
    && i.operands == 1
-   && i.tm.base_opcode == 0x30
-   && i.tm.extension_opcode == None)))))
+   && i.tm.base_opcode == 0x30)))))
     {
       /* Optimize: -O:
    andq $imm31, %r64   -> andl $imm31, %r32
@@ -4014,6 +4012,7 @@ optimize_encoding (void)
     }
   else if (optimize > 1
    && !optimize_for_space
+   && !is_any_vex_encoding (&i.tm)
    && i.reg_operands == 2
    && i.op[0].regs == i.op[1].regs
    && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8

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Re: [PATCH 0/3] x86: follow-on to ac0ab1842d

H.J. Lu-30
In reply to this post by Jan Beulich-2
On Mon, Dec 16, 2019 at 2:01 AM Jan Beulich <[hidden email]> wrote:
>
> 1: consistently convert to byte registers for TEST w/ imm optimization
> 2: assert sane internal state for REX conversions
> 3: refine when to trigger optimizations
>
> Jan

OK.

Thanks.


--
H.J.