J3 flash lockbits across reset

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J3 flash lockbits across reset

alfred hitch
Hi,

I am confused on what is the correct behavior across power resets
(of hardware) for J3 flash'es.

1) Will all sectors which were locked before power reset, remain so ?

I am confused by some posts on net, saying they get locked (all) by
default across resets (irr. of before power reset status)

Some say, it is unlocked (all blocks )by default  across resets.

I dont think flash should change status across resets. It should
preserve whatever I locked before reboot and vice versa.

2) Is it dependant on version, looking at j3 v d there seem to be a
bug on registers for same also which was fixed. Gives me an errie
feeling that responses on net were diff. because of people using diff.
kernels and flash revisions and so diff. observations ?

3) Intel FAQ says, that :

While setting up a Set Block Lock-Bit or Clear Block-Bits operation.
must the first and second bus cycles be sequential write operations
(i.e., no other bus operations to the flash between write cycles)?
For the Set and Clear Block Lock Bit operations, the first and second
bus cycles must be sequential. If the 28xxxJ3 receives any other
command during the second write cycle, an invalid command sequence
occurs. This causes the mode (the first bus cycle) to be aborted, and
bits 5 and 4 in the Status Register will be set.

So, will this effectively mean that I cannot use this lock / unlock
feature unless I can be sure there will be no read / write etc from
ANY flash location ? as this will break the WSM sequence ?

Sorry I am trying to design a feature (and dont have hardware to play
with) so looking to be sure.

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Re: J3 flash lockbits across reset

Andrew Lunn-2
On Thu, Jan 12, 2006 at 03:33:03AM -0500, alfred hitch wrote:

> Hi,
>
> I am confused on what is the correct behavior across power resets
> (of hardware) for J3 flash'es.
>
> 1) Will all sectors which were locked before power reset, remain so ?
>
> I am confused by some posts on net, saying they get locked (all) by
> default across resets (irr. of before power reset status)
>
> Some say, it is unlocked (all blocks )by default  across resets.
>
> I dont think flash should change status across resets. It should
> preserve whatever I locked before reboot and vice versa.

The data sheet for the chip is the best source of answer for this
question.

> 2) Is it dependant on version, looking at j3 v d there seem to be a
> bug on registers for same also which was fixed. Gives me an errie
> feeling that responses on net were diff. because of people using diff.
> kernels and flash revisions and so diff. observations ?

"kernels" are you talking "Linux" here? This is an eCos mailling list.
 

> 3) Intel FAQ says, that :
>
> While setting up a Set Block Lock-Bit or Clear Block-Bits operation.
> must the first and second bus cycles be sequential write operations
> (i.e., no other bus operations to the flash between write cycles)?
> For the Set and Clear Block Lock Bit operations, the first and second
> bus cycles must be sequential. If the 28xxxJ3 receives any other
> command during the second write cycle, an invalid command sequence
> occurs. This causes the mode (the first bus cycle) to be aborted, and
> bits 5 and 4 in the Status Register will be set.
>
> So, will this effectively mean that I cannot use this lock / unlock
> feature unless I can be sure there will be no read / write etc from
> ANY flash location ? as this will break the WSM sequence ?

It sounds like you need to ensure the functions to lock/unlock are
running from RAM and that you disable interrupts. Running from RAM is
easy to acheive, in fact all code which acts on the FLASH needs to do
this. Just cut&paste the attribute section statement. Most of the
flash drivers don't disable interrupts, but this is also easy to add
for your specific driver.
 
        Andrew

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Re: J3 flash lockbits across reset

alfred hitch
H Andrew,

1) I didnt see any where in data sheet clerly mentioning this info.
2) I was referring to versions of j3 chips and responses on net ..
nothing kernel specific. (kernel happened to be another variable in
this diff. response question)
3) Going to RAM is anyways needed.
My ques. was does one needs to ensure that there are no process which
issue a read / write to flash in parallel at the time 1st lock command
was issued.

Regards,
Alfred

On 1/12/06, Andrew Lunn <[hidden email]> wrote:

> On Thu, Jan 12, 2006 at 03:33:03AM -0500, alfred hitch wrote:
> > Hi,
> >
> > I am confused on what is the correct behavior across power resets
> > (of hardware) for J3 flash'es.
> >
> > 1) Will all sectors which were locked before power reset, remain so ?
> >
> > I am confused by some posts on net, saying they get locked (all) by
> > default across resets (irr. of before power reset status)
> >
> > Some say, it is unlocked (all blocks )by default  across resets.
> >
> > I dont think flash should change status across resets. It should
> > preserve whatever I locked before reboot and vice versa.
>
> The data sheet for the chip is the best source of answer for this
> question.
>
> > 2) Is it dependant on version, looking at j3 v d there seem to be a
> > bug on registers for same also which was fixed. Gives me an errie
> > feeling that responses on net were diff. because of people using diff.
> > kernels and flash revisions and so diff. observations ?
>
> "kernels" are you talking "Linux" here? This is an eCos mailling list.
>
> > 3) Intel FAQ says, that :
> >
> > While setting up a Set Block Lock-Bit or Clear Block-Bits operation.
> > must the first and second bus cycles be sequential write operations
> > (i.e., no other bus operations to the flash between write cycles)?
> > For the Set and Clear Block Lock Bit operations, the first and second
> > bus cycles must be sequential. If the 28xxxJ3 receives any other
> > command during the second write cycle, an invalid command sequence
> > occurs. This causes the mode (the first bus cycle) to be aborted, and
> > bits 5 and 4 in the Status Register will be set.
> >
> > So, will this effectively mean that I cannot use this lock / unlock
> > feature unless I can be sure there will be no read / write etc from
> > ANY flash location ? as this will break the WSM sequence ?
>
> It sounds like you need to ensure the functions to lock/unlock are
> running from RAM and that you disable interrupts. Running from RAM is
> easy to acheive, in fact all code which acts on the FLASH needs to do
> this. Just cut&paste the attribute section statement. Most of the
> flash drivers don't disable interrupts, but this is also easy to add
> for your specific driver.
>
>         Andrew
>

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Re: J3 flash lockbits across reset

Andrew Lunn-2
On Thu, Jan 12, 2006 at 04:36:52AM -0500, alfred hitch wrote:
> 3) Going to RAM is anyways needed.
> My ques. was does one needs to ensure that there are no process which
> issue a read / write to flash in parallel at the time 1st lock command
> was issued.

That is why i said disable interrupts. Apart from a NMI nothing else
can happen.

        Andrew

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Re: J3 flash lockbits across reset

Gary Thomas
In reply to this post by Andrew Lunn-2
On Thu, 2006-01-12 at 09:44 +0100, Andrew Lunn wrote:

> On Thu, Jan 12, 2006 at 03:33:03AM -0500, alfred hitch wrote:
> > Hi,
> >
> > I am confused on what is the correct behavior across power resets
> > (of hardware) for J3 flash'es.
> >
> > 1) Will all sectors which were locked before power reset, remain so ?
> >
> > I am confused by some posts on net, saying they get locked (all) by
> > default across resets (irr. of before power reset status)
> >
> > Some say, it is unlocked (all blocks )by default  across resets.
> >
> > I dont think flash should change status across resets. It should
> > preserve whatever I locked before reboot and vice versa.
>
> The data sheet for the chip is the best source of answer for this
> question.
>

The J3 devices are different from most other FLASH devices - all
sectors are *always* locked after a device reset.  This is just how
the hardware works.

--
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------


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RE: J3 flash lockbits across reset

Stephen Goadhouse
> -----Original Message-----
> From: [hidden email]
> [mailto:[hidden email]] On Behalf Of
> Gary Thomas
> Sent: Thursday, January 12, 2006 8:22 AM
> To: Andrew Lunn
> Cc: alfred hitch; eCos Discussion
> Subject: Re: [ECOS] J3 flash lockbits across reset
>
> On Thu, 2006-01-12 at 09:44 +0100, Andrew Lunn wrote:
> > On Thu, Jan 12, 2006 at 03:33:03AM -0500, alfred hitch wrote:
> > > Hi,
> > >
> > > I am confused on what is the correct behavior across power resets
> > > (of hardware) for J3 flash'es.
> > >
> > > 1) Will all sectors which were locked before power reset,
> remain so ?
> > >
> > > I am confused by some posts on net, saying they get
> locked (all) by
> > > default across resets (irr. of before power reset status)
> > >
> > > Some say, it is unlocked (all blocks )by default  across resets.
> > >
> > > I dont think flash should change status across resets. It should
> > > preserve whatever I locked before reboot and vice versa.
> >
> > The data sheet for the chip is the best source of answer for this
> > question.
> >
>
> The J3 devices are different from most other FLASH devices -
> all sectors are *always* locked after a device reset.  This
> is just how the hardware works.
>
> --
> ------------------------------------------------------------
> Gary Thomas                 |  Consulting for the
> MLB Associates              |    Embedded world
> ------------------------------------------------------------

This is incorrect.  You must be thinking of the new Intel P30 Flash.  For
the old reliable J3 Flash, the lock bits are stored in non-volatile Flash
cells and survive a reset/power cycle.  If you lock a sector in J3 Flash,
it stays locked, through resets and power cycles, until the "unlock all
sectors" command is given.

The new Intel P30 Flash is like you describe.  The lock bits are stored
in volatile memory. All sectors are in the lock state whenever you reset
the chip or power cycle. Any sectors that you unlocked will not be
remembered through resets/power cycles.  You have to always unlock
sectors before writing to them.  It's a super pain!  Apparently some
older Intel Flash series also did this and for some reason they brought
back this stupid feature.  It totally goes against what RedBoot expects
from Flash.


_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/  
_/  Stephen Goadhouse                 Work: (434) 978-2888 x254 _/
_/  Senior Staff Engineer  [hidden email] _/
_/  ADI Engineering               http://www.adiengineering.com _/
_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/



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RE: J3 flash lockbits across reset

Gary Thomas
On Thu, 2006-01-12 at 08:40 -0500, Stephen Goadhouse wrote:

> > -----Original Message-----
> > From: [hidden email]
> > [mailto:[hidden email]] On Behalf Of
> > Gary Thomas
> > Sent: Thursday, January 12, 2006 8:22 AM
> > To: Andrew Lunn
> > Cc: alfred hitch; eCos Discussion
> > Subject: Re: [ECOS] J3 flash lockbits across reset
> >
> > On Thu, 2006-01-12 at 09:44 +0100, Andrew Lunn wrote:
> > > On Thu, Jan 12, 2006 at 03:33:03AM -0500, alfred hitch wrote:
> > > > Hi,
> > > >
> > > > I am confused on what is the correct behavior across power resets
> > > > (of hardware) for J3 flash'es.
> > > >
> > > > 1) Will all sectors which were locked before power reset,
> > remain so ?
> > > >
> > > > I am confused by some posts on net, saying they get
> > locked (all) by
> > > > default across resets (irr. of before power reset status)
> > > >
> > > > Some say, it is unlocked (all blocks )by default  across resets.
> > > >
> > > > I dont think flash should change status across resets. It should
> > > > preserve whatever I locked before reboot and vice versa.
> > >
> > > The data sheet for the chip is the best source of answer for this
> > > question.
> > >
> >
> > The J3 devices are different from most other FLASH devices -
> > all sectors are *always* locked after a device reset.  This
> > is just how the hardware works.

>
> This is incorrect.  You must be thinking of the new Intel P30 Flash.  For
> the old reliable J3 Flash, the lock bits are stored in non-volatile Flash
> cells and survive a reset/power cycle.  If you lock a sector in J3 Flash,
> it stays locked, through resets and power cycles, until the "unlock all
> sectors" command is given.
>
> The new Intel P30 Flash is like you describe.  The lock bits are stored
> in volatile memory. All sectors are in the lock state whenever you reset
> the chip or power cycle. Any sectors that you unlocked will not be
> remembered through resets/power cycles.  You have to always unlock
> sectors before writing to them.  It's a super pain!  Apparently some
> older Intel Flash series also did this and for some reason they brought
> back this stupid feature.  It totally goes against what RedBoot expects
> from Flash.

Sorry, you are correct (I recently did some work with the P30 FLASH
devices and they were fresh in my mind, just not the moniker)

--
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------


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