Improve MIPS soft-float support

classic Classic list List threaded Threaded
2 messages Options
Reply | Threaded
Open this post in threaded view
|

Improve MIPS soft-float support

Joseph Myers
This patch improves support for a MIPS soft-float configuration.  In such
a configuration, setjmp/longjmp/fpu_control.h shouldn't be using
floating-point registers.

(The fpu_control.h changes make it act like sysdeps/generic/fpu_control.h
in the soft-float case.  Moving the header to sysdeps/mips/fpu would be a
bad idea since then you couldn't use the same installed headers for both
hard and soft float configurations.)

2006-09-01  Joseph Myers  <[hidden email]>

        * sysdeps/mips/fpu_control.h: If soft-float, don't use
        floating-point registers.
        * sysdeps/mips/__longjmp.c, sysdeps/mips/setjmp_aux.c,
        sysdeps/mips/mips64/__longjmp.c, sysdeps/mips/mips64/setjmp_aux.c:
        Likewise.

Index: sysdeps/mips/__longjmp.c
===================================================================
RCS file: /cvs/glibc/ports/sysdeps/mips/__longjmp.c,v
retrieving revision 1.9
diff -u -r1.9 __longjmp.c
--- sysdeps/mips/__longjmp.c 6 Jul 2001 04:56:00 -0000 1.9
+++ sysdeps/mips/__longjmp.c 1 Sep 2006 14:26:49 -0000
@@ -37,6 +37,7 @@
      along the way.  */
   register int val asm ("a1");
 
+#ifdef __mips_hard_float
   /* Pull back the floating point callee-saved registers.  */
   asm volatile ("l.d $f20, %0" : : "m" (env[0].__fpregs[0]));
   asm volatile ("l.d $f22, %0" : : "m" (env[0].__fpregs[1]));
@@ -48,6 +49,7 @@
   /* Get and reconstruct the floating point csr.  */
   asm volatile ("lw $2, %0" : : "m" (env[0].__fpc_csr));
   asm volatile ("ctc1 $2, $31");
+#endif
 
   /* Get the GP. */
   asm volatile ("lw $gp, %0" : : "m" (env[0].__gp));
Index: sysdeps/mips/fpu_control.h
===================================================================
RCS file: /cvs/glibc/ports/sysdeps/mips/fpu_control.h,v
retrieving revision 1.6
diff -u -r1.6 fpu_control.h
--- sysdeps/mips/fpu_control.h 6 Jul 2001 04:56:00 -0000 1.6
+++ sysdeps/mips/fpu_control.h 1 Sep 2006 14:26:49 -0000
@@ -58,6 +58,17 @@
 
 #include <features.h>
 
+#ifdef __mips_soft_float
+
+#define _FPU_RESERVED 0xffffffff
+#define _FPU_DEFAULT  0x00000000
+typedef unsigned int fpu_control_t;
+#define _FPU_GETCW(cw) 0
+#define _FPU_SETCW(cw) do { } while (0)
+extern fpu_control_t __fpu_control;
+
+#else /* __mips_soft_float */
+
 /* masking of interrupts */
 #define _FPU_MASK_V     0x0800  /* Invalid operation */
 #define _FPU_MASK_Z     0x0400  /* Division by zero  */
@@ -95,4 +106,6 @@
 /* Default control word set at startup.  */
 extern fpu_control_t __fpu_control;
 
+#endif /* __mips_soft_float */
+
 #endif /* fpu_control.h */
Index: sysdeps/mips/setjmp_aux.c
===================================================================
RCS file: /cvs/glibc/ports/sysdeps/mips/setjmp_aux.c,v
retrieving revision 1.10
diff -u -r1.10 setjmp_aux.c
--- sysdeps/mips/setjmp_aux.c 20 Mar 2003 10:27:55 -0000 1.10
+++ sysdeps/mips/setjmp_aux.c 1 Sep 2006 14:26:49 -0000
@@ -27,6 +27,7 @@
 int
 __sigsetjmp_aux (jmp_buf env, int savemask, int sp, int fp)
 {
+#ifdef __mips_hard_float
   /* Store the floating point callee-saved registers...  */
   asm volatile ("s.d $f20, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[0]));
   asm volatile ("s.d $f22, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[1]));
@@ -34,6 +35,7 @@
   asm volatile ("s.d $f26, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[3]));
   asm volatile ("s.d $f28, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[4]));
   asm volatile ("s.d $f30, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[5]));
+#endif
 
   /* .. and the PC;  */
   asm volatile ("sw $31, %0" : : "m" (env[0].__jmpbuf[0].__pc));
@@ -57,8 +59,10 @@
   asm volatile ("sw $22, %0" : : "m" (env[0].__jmpbuf[0].__regs[6]));
   asm volatile ("sw $23, %0" : : "m" (env[0].__jmpbuf[0].__regs[7]));
 
+#ifdef __mips_hard_float
   /* .. and finally get and reconstruct the floating point csr.  */
   asm ("cfc1 %0, $31" : "=r" (env[0].__jmpbuf[0].__fpc_csr));
+#endif
 
   /* Save the signal mask if requested.  */
   return __sigjmp_save (env, savemask);
Index: sysdeps/mips/mips64/__longjmp.c
===================================================================
RCS file: /cvs/glibc/ports/sysdeps/mips/mips64/__longjmp.c,v
retrieving revision 1.7
diff -u -r1.7 __longjmp.c
--- sysdeps/mips/mips64/__longjmp.c 24 Nov 2004 04:36:10 -0000 1.7
+++ sysdeps/mips/mips64/__longjmp.c 1 Sep 2006 14:26:49 -0000
@@ -39,6 +39,7 @@
      along the way.  */
   register int val asm ("a1");
 
+#ifdef __mips_hard_float
   /* Pull back the floating point callee-saved registers.  */
 #if _MIPS_SIM == _ABI64
   asm volatile ("l.d $f24, %0" : : "m" (env[0].__fpregs[0]));
@@ -61,6 +62,7 @@
   /* Get and reconstruct the floating point csr.  */
   asm volatile ("lw $2, %0" : : "m" (env[0].__fpc_csr));
   asm volatile ("ctc1 $2, $31");
+#endif
 
   /* Get the GP. */
   asm volatile ("ld $gp, %0" : : "m" (env[0].__gp));
Index: sysdeps/mips/mips64/setjmp_aux.c
===================================================================
RCS file: /cvs/glibc/ports/sysdeps/mips/mips64/setjmp_aux.c,v
retrieving revision 1.6
diff -u -r1.6 setjmp_aux.c
--- sysdeps/mips/mips64/setjmp_aux.c 24 Nov 2004 04:36:10 -0000 1.6
+++ sysdeps/mips/mips64/setjmp_aux.c 1 Sep 2006 14:26:49 -0000
@@ -29,6 +29,7 @@
 __sigsetjmp_aux (jmp_buf env, int savemask, long long sp, long long fp,
  long long gp)
 {
+#ifdef __mips_hard_float
   /* Store the floating point callee-saved registers...  */
 #if _MIPS_SIM == _ABI64
   asm volatile ("s.d $f24, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[0]));
@@ -47,6 +48,7 @@
   asm volatile ("s.d $f28, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[4]));
   asm volatile ("s.d $f30, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[5]));
 #endif
+#endif
 
   /* .. and the PC;  */
   asm volatile ("sd $31, %0" : : "m" (env[0].__jmpbuf[0].__pc));
@@ -70,8 +72,10 @@
   asm volatile ("sd $22, %0" : : "m" (env[0].__jmpbuf[0].__regs[6]));
   asm volatile ("sd $23, %0" : : "m" (env[0].__jmpbuf[0].__regs[7]));
 
+#ifdef __mips_hard_float
   /* .. and finally get and reconstruct the floating point csr.  */
   asm ("cfc1 %0, $31" : "=r" (env[0].__jmpbuf[0].__fpc_csr));
+#endif
 
   /* Save the signal mask if requested.  */
   return __sigjmp_save (env, savemask);

--
Joseph S. Myers
[hidden email]
Reply | Threaded
Open this post in threaded view
|

Re: Improve MIPS soft-float support

Daniel Jacobowitz-2
On Fri, Sep 01, 2006 at 02:30:26PM +0000, Joseph S. Myers wrote:

> This patch improves support for a MIPS soft-float configuration.  In such
> a configuration, setjmp/longjmp/fpu_control.h shouldn't be using
> floating-point registers.
>
> (The fpu_control.h changes make it act like sysdeps/generic/fpu_control.h
> in the soft-float case.  Moving the header to sysdeps/mips/fpu would be a
> bad idea since then you couldn't use the same installed headers for both
> hard and soft float configurations.)
>
> 2006-09-01  Joseph Myers  <[hidden email]>
>
> * sysdeps/mips/fpu_control.h: If soft-float, don't use
> floating-point registers.
> * sysdeps/mips/__longjmp.c, sysdeps/mips/setjmp_aux.c,
> sysdeps/mips/mips64/__longjmp.c, sysdeps/mips/mips64/setjmp_aux.c:
> Likewise.

Thanks, applied.

--
Daniel Jacobowitz
CodeSourcery