[COMMITTED, BPF] cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions

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[COMMITTED, BPF] cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions

Jose E. Marchesi-2

Hi people!

Yet another correction for the eBPF non-generic loads.  Now it is the
turn of the absolute load instructions, that take an imm32 immediate
only, and whose apparent purpose is to complement the ldind instructions
like:

  ldind{b,h,w,dw} %src,imm32  -->  loads from skb[%src+imm32]
  ldabs{b,h,w,dw} imm32       -->  loads from skb[imm32]

The joys of not having a "zero" register in the architecture I
guess... :/

Salud!

commit 3719fd55b6f89662653d50d33bb267c5f21127a5
Author: Jose E. Marchesi <[hidden email]>
Date:   Mon Jul 15 16:00:28 2019 +0200

    cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructions
   
    This patch fixes the eBPF CPU description in order to reflect the
    right explicit arguments passed to the ldabs{b,h,w,dw} instructions,
    updates the corresponding GAS tests, and updates the BPF section of
    the GAS manual.
   
    cpu/ChangeLog:
   
    2019-07-15  Jose E. Marchesi  <[hidden email]>
   
            * bpf.cpu (dlabs): New pmacro.
            (dlind): Likewise.
   
    opcodes/ChangeLog:
   
    2019-07-15  Jose E. Marchesi  <[hidden email]>
   
            * bpf-desc.c: Regenerate.
            * bpf-opc.c: Likewise.
            * bpf-opc.h: Likewise.
   
    gas/ChangeLog:
   
    2019-07-15  Jose E. Marchesi  <[hidden email]>
   
            * testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
            register as an argument.
            * testsuite/gas/bpf/mem.d: Updated accordingly.
            * testsuite/gas/bpf/mem-be.d: Likewise.
            * doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
            explicit arguments to ldabs and ldind instructions.

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 49940034bb..41d008f0e1 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,8 @@
+2019-07-15  Jose E. Marchesi  <[hidden email]>
+
+ * bpf.cpu (dlabs): New pmacro.
+ (dlind): Likewise.
+
 2019-07-14  Jose E. Marchesi  <[hidden email]>
 
  * bpf.cpu (dlsi): ldabs and ldind instructions do not take an
diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu
index 60e89fb71c..b8a3a92e66 100644
--- a/cpu/bpf.cpu
+++ b/cpu/bpf.cpu
@@ -466,36 +466,49 @@
 (define-lddw le)
 (define-lddw be)
 
-;; The absolute/indirect load instructions are non-generic loads
-;; designed to be used in socket filters.  They come in several
-;; variants:
+;; The absolute load instructions are non-generic loads designed to be
+;; used in socket filters.  They come in several variants:
+;;
+;; LDABS{w,h,b,dw}
+
+(define-pmacro (dlabs x-suffix x-size)
+  (dni (.sym "ldabs" x-suffix)
+       (.str "ldabs" x-suffix)
+       (all-isas)
+       (.str "ldabs" x-suffix " $imm32")
+       (+ imm32 (f-offset16 0) (f-regs 0)
+          OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
+       () ()))
+
+(dlabs "w" W)
+(dlabs "h" H)
+(dlabs "b" B)
+(dlabs "dw" DW)
+
+;; The indirect load instructions are non-generic loads designed to be
+;; used in socket filters.  They come in several variants:
 ;;
-;; LD{abs,ind}{w,h,b,dw}le for the little-endian ISA
-;; LD{abs,ind}[w,h,b,dw}be for the big-endian ISA
+;; LDIND{w,h,b,dw}le for the little-endian ISA
+;; LDIND[w,h,b,dw}be for the big-endian ISA
 
-(define-pmacro (dlsi x-basename x-suffix x-class x-size x-mode x-endian)
-  (dni (.sym x-basename x-suffix x-endian)
-       (.str x-basename x-suffix)
+(define-pmacro (dlind x-suffix x-size x-endian)
+  (dni (.sym "ldind" x-suffix x-endian)
+       (.str "ldind" x-suffix)
        ((ISA (.sym ebpf x-endian)))
-       (.str x-basename x-suffix " $src" x-endian ",$imm32")
+       (.str "ldind" x-suffix " $src" x-endian ",$imm32")
        (+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
-          (.sym OP_CLASS_ x-class) (.sym OP_SIZE_ x-size)
-          (.sym OP_MODE_ x-mode)) () ()))
+          OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
+       () ()))
 
-(define-pmacro (define-ldabsind x-endian)
-  (begin
-    (dlsi "ldabs" "w" LD W ABS x-endian)
-    (dlsi "ldabs" "h" LD H ABS x-endian)
-    (dlsi "ldabs" "b" LD B ABS x-endian)
-    (dlsi "ldabs" "dw" LD DW ABS x-endian)
-    
-    (dlsi "ldind" "w" LD W IND x-endian)
-    (dlsi "ldind" "h" LD H IND x-endian)
-    (dlsi "ldind" "b" LD B IND x-endian)
-    (dlsi "ldind" "dw" LD DW IND x-endian)))
-
-(define-ldabsind le)
-(define-ldabsind be)
+(define-pmacro (define-ldind x-endian)
+  (begin    
+    (dlind "w" W x-endian)
+    (dlind "h" H x-endian)
+    (dlind "b" B x-endian)
+    (dlind "dw" DW x-endian)))
+
+(define-ldind le)
+(define-ldind be)
 
 ;; Generic load and store instructions are provided for several word
 ;; sizes.  They come in several variants:
diff --git a/gas/ChangeLog b/gas/ChangeLog
index fb44aa3d6f..2d8a99724a 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2019-07-15  Jose E. Marchesi  <[hidden email]>
+
+ * testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
+ register as an argument.
+ * testsuite/gas/bpf/mem.d: Updated accordingly.
+ * testsuite/gas/bpf/mem-be.d: Likewise.
+ * doc/c-bpf.texi (BPF Opcodes): Update to reflect the correct
+ explicit arguments to ldabs and ldind instructions.
+
 2019-07-14  Jose E. Marchesi  <[hidden email]>
 
  * testsuite/gas/bpf/mem.s: Do not use explicit arguments for
diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi
index a7a694f3bd..13f41441ca 100644
--- a/gas/doc/c-bpf.texi
+++ b/gas/doc/c-bpf.texi
@@ -234,26 +234,26 @@ tree for more information.
 Absolute loads:
 
 @table @code
-@item ldabsdw %d, %s, imm32
+@item ldabsdw imm32
 Absolute 64-bit load.
-@item ldabsw %d, %s, imm32
+@item ldabsw imm32
 Absolute 32-bit load.
-@item ldabsh %d, %s, imm32
+@item ldabsh imm32
 Absolute 16-bit load.
-@item ldabsb %d, %s, imm32
+@item ldabsb imm32
 Absolute 8-bit load.
 @end table
 
 Indirect loads:
 
 @table @code
-@item ldinddw %d, %s, imm32
+@item ldinddw %s, imm32
 Indirect 64-bit load.
-@item ldindw %d, %s, imm32
+@item ldindw %s, imm32
 Indirect 32-bit load.
-@item ldindh %d, %s, imm32
+@item ldindh %s, imm32
 Indirect 16-bit load.
-@item ldindb %d, %s, imm32
+@item ldindb %s, imm32
 Indirect 8-bit load.
 @end table
 
diff --git a/gas/testsuite/gas/bpf/mem-be.d b/gas/testsuite/gas/bpf/mem-be.d
index 7a258bcd55..b3dba80c2b 100644
--- a/gas/testsuite/gas/bpf/mem-be.d
+++ b/gas/testsuite/gas/bpf/mem-be.d
@@ -8,10 +8,10 @@
 Disassembly of section .text:
 
 0+ <.text>:
-   0: 20 03 00 00 00 00 be ef ldabsw %r3,0xbeef
-   8: 28 05 00 00 00 00 be ef ldabsh %r5,0xbeef
-  10: 30 07 00 00 00 00 be ef ldabsb %r7,0xbeef
-  18: 38 09 00 00 00 00 be ef ldabsdw %r9,0xbeef
+   0: 20 00 00 00 00 00 be ef ldabsw 0xbeef
+   8: 28 00 00 00 00 00 be ef ldabsh 0xbeef
+  10: 30 00 00 00 00 00 be ef ldabsb 0xbeef
+  18: 38 00 00 00 00 00 be ef ldabsdw 0xbeef
   20: 40 03 00 00 00 00 be ef ldindw %r3,0xbeef
   28: 48 05 00 00 00 00 be ef ldindh %r5,0xbeef
   30: 50 07 00 00 00 00 be ef ldindb %r7,0xbeef
diff --git a/gas/testsuite/gas/bpf/mem.d b/gas/testsuite/gas/bpf/mem.d
index 4587ffdbe7..0e0b498ea9 100644
--- a/gas/testsuite/gas/bpf/mem.d
+++ b/gas/testsuite/gas/bpf/mem.d
@@ -7,10 +7,10 @@
 Disassembly of section .text:
 
 0+ <.text>:
-   0: 20 30 00 00 ef be 00 00 ldabsw %r3,0xbeef
-   8: 28 50 00 00 ef be 00 00 ldabsh %r5,0xbeef
-  10: 30 70 00 00 ef be 00 00 ldabsb %r7,0xbeef
-  18: 38 90 00 00 ef be 00 00 ldabsdw %r9,0xbeef
+   0: 20 00 00 00 ef be 00 00 ldabsw 0xbeef
+   8: 28 00 00 00 ef be 00 00 ldabsh 0xbeef
+  10: 30 00 00 00 ef be 00 00 ldabsb 0xbeef
+  18: 38 00 00 00 ef be 00 00 ldabsdw 0xbeef
   20: 40 30 00 00 ef be 00 00 ldindw %r3,0xbeef
   28: 48 50 00 00 ef be 00 00 ldindh %r5,0xbeef
   30: 50 70 00 00 ef be 00 00 ldindb %r7,0xbeef
diff --git a/gas/testsuite/gas/bpf/mem.s b/gas/testsuite/gas/bpf/mem.s
index f0f1d08e20..af6f41b0db 100644
--- a/gas/testsuite/gas/bpf/mem.s
+++ b/gas/testsuite/gas/bpf/mem.s
@@ -2,10 +2,10 @@
 
         .text
 
- ldabsw %r3, 0xbeef
- ldabsh %r5, 0xbeef
- ldabsb %r7, 0xbeef
- ldabsdw %r9, 0xbeef
+ ldabsw 0xbeef
+ ldabsh 0xbeef
+ ldabsb 0xbeef
+ ldabsdw 0xbeef
  ldindw %r3, 0xbeef
  ldindh %r5, 0xbeef
  ldindb %r7, 0xbeef
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e1de65b5d4..c00cb8adf5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2019-07-15  Jose E. Marchesi  <[hidden email]>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.c: Likewise.
+ * bpf-opc.h: Likewise.
+
 2019-07-14  Jose E. Marchesi  <[hidden email]>
 
  * bpf-desc.c: Regenerate.
diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c
index 3b943353dc..18ded6e797 100644
--- a/opcodes/bpf-desc.c
+++ b/opcodes/bpf-desc.c
@@ -824,25 +824,25 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
     BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
   },
-/* ldabsw $srcle,$imm32 */
+/* ldabsw $imm32 */
   {
-    BPF_INSN_LDABSWLE, "ldabswle", "ldabsw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
   },
-/* ldabsh $srcle,$imm32 */
+/* ldabsh $imm32 */
   {
-    BPF_INSN_LDABSHLE, "ldabshle", "ldabsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
   },
-/* ldabsb $srcle,$imm32 */
+/* ldabsb $imm32 */
   {
-    BPF_INSN_LDABSBLE, "ldabsble", "ldabsb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
   },
-/* ldabsdw $srcle,$imm32 */
+/* ldabsdw $imm32 */
   {
-    BPF_INSN_LDABSDWLE, "ldabsdwle", "ldabsdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
   },
 /* ldindw $srcle,$imm32 */
   {
@@ -864,26 +864,6 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
     BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
   },
-/* ldabsw $srcbe,$imm32 */
-  {
-    BPF_INSN_LDABSWBE, "ldabswbe", "ldabsw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
-  },
-/* ldabsh $srcbe,$imm32 */
-  {
-    BPF_INSN_LDABSHBE, "ldabshbe", "ldabsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
-  },
-/* ldabsb $srcbe,$imm32 */
-  {
-    BPF_INSN_LDABSBBE, "ldabsbbe", "ldabsb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
-  },
-/* ldabsdw $srcbe,$imm32 */
-  {
-    BPF_INSN_LDABSDWBE, "ldabsdwbe", "ldabsdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
-  },
 /* ldindw $srcbe,$imm32 */
   {
     BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index 4a36cb9714..7707aaa0da 100644
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -89,11 +89,15 @@ static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
   8, 128, 0xff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ldabswle ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {
+  8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {
   8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
 };
 
-static const CGEN_IFMT ifmt_ldabswbe ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {
   8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
 };
 
@@ -792,101 +796,77 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DSTBE), ',', OP (IMM64), 0 } },
     & ifmt_lddwbe, { 0x18 }
   },
-/* ldabsw $srcle,$imm32 */
+/* ldabsw $imm32 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x20 }
+    { { MNEM, ' ', OP (IMM32), 0 } },
+    & ifmt_ldabsw, { 0x20 }
   },
-/* ldabsh $srcle,$imm32 */
+/* ldabsh $imm32 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x28 }
+    { { MNEM, ' ', OP (IMM32), 0 } },
+    & ifmt_ldabsw, { 0x28 }
   },
-/* ldabsb $srcle,$imm32 */
+/* ldabsb $imm32 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x30 }
+    { { MNEM, ' ', OP (IMM32), 0 } },
+    & ifmt_ldabsw, { 0x30 }
   },
-/* ldabsdw $srcle,$imm32 */
+/* ldabsdw $imm32 */
   {
     { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x38 }
+    { { MNEM, ' ', OP (IMM32), 0 } },
+    & ifmt_ldabsw, { 0x38 }
   },
 /* ldindw $srcle,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x40 }
+    & ifmt_ldindwle, { 0x40 }
   },
 /* ldindh $srcle,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x48 }
+    & ifmt_ldindwle, { 0x48 }
   },
 /* ldindb $srcle,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x50 }
+    & ifmt_ldindwle, { 0x50 }
   },
 /* ldinddw $srcle,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswle, { 0x58 }
-  },
-/* ldabsw $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x20 }
-  },
-/* ldabsh $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x28 }
-  },
-/* ldabsb $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x30 }
-  },
-/* ldabsdw $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x38 }
+    & ifmt_ldindwle, { 0x58 }
   },
 /* ldindw $srcbe,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x40 }
+    & ifmt_ldindwbe, { 0x40 }
   },
 /* ldindh $srcbe,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x48 }
+    & ifmt_ldindwbe, { 0x48 }
   },
 /* ldindb $srcbe,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x50 }
+    & ifmt_ldindwbe, { 0x50 }
   },
 /* ldinddw $srcbe,$imm32 */
   {
     { 0, 0, 0, 0 },
     { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldabswbe, { 0x58 }
+    & ifmt_ldindwbe, { 0x58 }
   },
 /* ldxw $dstle,[$srcle+$offset16] */
   {
diff --git a/opcodes/bpf-opc.h b/opcodes/bpf-opc.h
index b989d7f031..a2cdc7c5ed 100644
--- a/opcodes/bpf-opc.h
+++ b/opcodes/bpf-opc.h
@@ -74,10 +74,9 @@ typedef enum cgen_insn_type {
  , BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE, BPF_INSN_MOV32RBE, BPF_INSN_ARSHIBE
  , BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_NEGBE
  , BPF_INSN_NEG32BE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
- , BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSWLE
- , BPF_INSN_LDABSHLE, BPF_INSN_LDABSBLE, BPF_INSN_LDABSDWLE, BPF_INSN_LDINDWLE
- , BPF_INSN_LDINDHLE, BPF_INSN_LDINDBLE, BPF_INSN_LDINDDWLE, BPF_INSN_LDABSWBE
- , BPF_INSN_LDABSHBE, BPF_INSN_LDABSBBE, BPF_INSN_LDABSDWBE, BPF_INSN_LDINDWBE
+ , BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSW
+ , BPF_INSN_LDABSH, BPF_INSN_LDABSB, BPF_INSN_LDABSDW, BPF_INSN_LDINDWLE
+ , BPF_INSN_LDINDHLE, BPF_INSN_LDINDBLE, BPF_INSN_LDINDDWLE, BPF_INSN_LDINDWBE
  , BPF_INSN_LDINDHBE, BPF_INSN_LDINDBBE, BPF_INSN_LDINDDWBE, BPF_INSN_LDXWLE
  , BPF_INSN_LDXHLE, BPF_INSN_LDXBLE, BPF_INSN_LDXDWLE, BPF_INSN_STXWLE
  , BPF_INSN_STXHLE, BPF_INSN_STXBLE, BPF_INSN_STXDWLE, BPF_INSN_LDXWBE