Add support for Intel TSXLDTRK instructions

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Add support for Intel TSXLDTRK instructions

Sourceware - binutils list mailing list
Hi all,

This patch is about to enable binutils support for TSXLDTRK which would

be in GLC. There's only 2 instructions: XRESLDTRK, XSUSLDTRK, more

details please refer to

https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf



Make check-gas is ok.


gas/ChangeLog:

              2020-04-02  Lili Cui  <[hidden email]>
              * config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
              (cpu_noarch): Likewise.
              * doc/c-i386.texi: Document TSXLDTRK.
              * testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
              * testsuite/gas/i386/tsxldtrk.d: Likewise.
              * testsuite/gas/i386/tsxldtrk.s: Likewise.

opcodes/gas/ChangeLog:

              2020-04-02  Lili Cui  <[hidden email]>
              * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
              (prefix_table): New instructions (see prefixes above).
              (rm_table): Likewise
              * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
              CPU_ANY_TSXLDTRK_FLAGS.
              (cpu_flags): Add CpuTSXLDTRK.
              * i386-opc.h (enum): Add CpuTSXLDTRK.
              (i386_cpu_flags): Add cputsxldtrk.
              * i386-opc.tbl: Add XSUSPLDTRK insns.
              * i386-init.h: Regenerate.
              * i386-tbl.h: Likewise.
---
gas/config/tc-i386.c              |  3 +++
gas/doc/c-i386.texi               |  4 +++-
gas/testsuite/gas/i386/i386.exp   |  1 +
gas/testsuite/gas/i386/tsxldtrk.d | 13 +++++++++++++
gas/testsuite/gas/i386/tsxldtrk.s |  7 +++++++
opcodes/i386-dis.c                | 13 ++++++++++++-
opcodes/i386-gen.c                |  5 +++++
opcodes/i386-opc.h                |  3 +++
opcodes/i386-opc.tbl              |  7 +++++++
9 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 gas/testsuite/gas/i386/tsxldtrk.d
create mode 100644 gas/testsuite/gas/i386/tsxldtrk.s

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 09063f784b..ac5210a42d 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1212,6 +1212,8 @@ static const arch_entry cpu_arch[] =
     CPU_MCOMMIT_FLAGS, 0 },
   { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN,
     CPU_SEV_ES_FLAGS, 0 },
+  { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN,
+    CPU_TSXLDTRK_FLAGS, 0 },
};
 static const noarch_entry cpu_noarch[] =
@@ -1255,6 +1257,7 @@ static const noarch_entry cpu_noarch[] =
   { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
   { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS },
   { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
+  { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS },
};
 #ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 1dd99f91bb..7f899c2874 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -187,6 +187,7 @@ accept various extension mnemonics.  For example,
@code{movdiri},
@code{movdir64b},
@code{enqcmd},
+@code{tsxldtrk},
@code{avx512f},
@code{avx512cd},
@code{avx512er},
@@ -221,6 +222,7 @@ accept various extension mnemonics.  For example,
@code{noavx512_vp2intersect},
@code{noavx512_bf16},
@code{noenqcmd},
+@code{notsxldtrk},
@code{vmx},
@code{vmfunc},
@code{smx},
@@ -1493,7 +1495,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
-@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd}
+@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index f21131ed99..3c47239b45 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -476,6 +476,7 @@ if [expr ([istarget "i*86-*-*"] ||  [istarget "x86_64-*-*"]) && [gas_32_check]]
     run_dump_test "enqcmd"
     run_dump_test "enqcmd-intel"
     run_list_test "enqcmd-inval"
+    run_dump_test "tsxldtrk"
     run_dump_test "vp2intersect"
     run_dump_test "vp2intersect-intel"
     run_list_test "vp2intersect-inval-bcast"
diff --git a/gas/testsuite/gas/i386/tsxldtrk.d b/gas/testsuite/gas/i386/tsxldtrk.d
new file mode 100644
index 0000000000..26df4ca633
--- /dev/null
+++ b/gas/testsuite/gas/i386/tsxldtrk.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: TSXLDTRK insns
+#source: tsxldtrk.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+ +[a-f0-9]+:      f2 0f 01 e8                        xsuspldtrk[         ]*
+ +[a-f0-9]+:      f2 0f 01 e9                        xresldtrk[            ]*
+#pass
diff --git a/gas/testsuite/gas/i386/tsxldtrk.s b/gas/testsuite/gas/i386/tsxldtrk.s
new file mode 100644
index 0000000000..3532c70a28
--- /dev/null
+++ b/gas/testsuite/gas/i386/tsxldtrk.s
@@ -0,0 +1,7 @@
+# Check TSXLDTRK instructions.
+
+            .text
+_start:
+            xsuspldtrk
+            xresldtrk
+
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 4a59619da4..12739389de 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -962,6 +962,7 @@ enum
   PREFIX_0F01_REG_3_RM_1,
   PREFIX_0F01_REG_5_MOD_0,
   PREFIX_0F01_REG_5_MOD_3_RM_0,
+  PREFIX_0F01_REG_5_MOD_3_RM_1,
   PREFIX_0F01_REG_5_MOD_3_RM_2,
   PREFIX_0F01_REG_7_MOD_3_RM_2,
   PREFIX_0F01_REG_7_MOD_3_RM_3,
@@ -3646,6 +3647,16 @@ static const struct dis386 prefix_table[][4] = {
   {
     { Bad_Opcode },
     { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
+    { Bad_Opcode },
+    { "xsuspldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
+  },
+
+  /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
   },
   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
@@ -11038,7 +11049,7 @@ static const struct dis386 rm_table[][8] = {
   {
     /* RM_0F01_REG_5_MOD_3 */
     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
     { Bad_Opcode },
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 50dd2b6f19..fef1713d7b 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -311,6 +311,8 @@ static initializer cpu_flag_init[] =
     "CpuMCOMMIT" },
   { "CPU_SEV_ES_FLAGS",
     "CpuSEV_ES" },
+  { "CPU_TSXLDTRK_FLAGS",
+    "CpuTSXLDTRK"},
   { "CPU_ANY_X87_FLAGS",
     "CPU_ANY_287_FLAGS|Cpu8087" },
   { "CPU_ANY_287_FLAGS",
@@ -387,6 +389,8 @@ static initializer cpu_flag_init[] =
     "CpuENQCMD" },
   { "CPU_ANY_AVX512_VP2INTERSECT_FLAGS",
     "CpuAVX512_VP2INTERSECT" },
+  { "CPU_ANY_TSXLDTRK_FLAGS",
+    "CpuTSXLDTRK" },
};
 static initializer operand_type_init[] =
@@ -609,6 +613,7 @@ static bitfield cpu_flags[] =
   BITFIELD (CpuRDPRU),
   BITFIELD (CpuMCOMMIT),
   BITFIELD (CpuSEV_ES),
+  BITFIELD (CpuTSXLDTRK),
#ifdef CpuUnused
   BITFIELD (CpuUnused),
#endif
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 480c979d19..684c97b485 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -249,6 +249,8 @@ enum
   CpuMCOMMIT,
   /* SEV-ES instruction(s) required */
   CpuSEV_ES,
+  /* TSXLDTRK instruction required */
+  CpuTSXLDTRK,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
@@ -381,6 +383,7 @@ typedef union i386_cpu_flags
       unsigned int cpurdpru:1;
       unsigned int cpumcommit:1;
       unsigned int cpusev_es:1;
+      unsigned int cputsxldtrk:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
#ifdef CpuUnused
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 206447dc63..19db6c0b90 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4076,3 +4076,10 @@ mcommit, 0, 0xf30f01fa, None, 3, CpuMCOMMIT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_
rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
 // RDPRU instruction end
+
+// TSXLDTRK instructions.
+
+xsuspldtrk, 0, 0xf20f01e8, None, 3, CpuTSXLDTRK, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+xresldtrk, 0, 0xf20f01e9, None, 3, CpuTSXLDTRK, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// TSXLDTRK instructions end.
--


0001-Add-support-for-intel-TSXLDTRK-instructions.patch (10K) Download Attachment
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Re: Add support for Intel TSXLDTRK instructions

Sourceware - binutils list mailing list
On Wed, Apr 1, 2020 at 8:20 PM Cui, Lili via Binutils
<[hidden email]> wrote:

>
> Hi all,
>
> This patch is about to enable binutils support for TSXLDTRK which would
>
> be in GLC. There's only 2 instructions: XRESLDTRK, XSUSLDTRK, more
>
> details please refer to
>
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
>
>
> Make check-gas is ok.
>
>
> gas/ChangeLog:
>
>               2020-04-02  Lili Cui  <[hidden email]>
>               * config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
>               (cpu_noarch): Likewise.
>               * doc/c-i386.texi: Document TSXLDTRK.
>               * testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
>               * testsuite/gas/i386/tsxldtrk.d: Likewise.
>               * testsuite/gas/i386/tsxldtrk.s: Likewise.
>
> opcodes/gas/ChangeLog:
>
>               2020-04-02  Lili Cui  <[hidden email]>
>               * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
>               (prefix_table): New instructions (see prefixes above).
>               (rm_table): Likewise
>               * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
>               CPU_ANY_TSXLDTRK_FLAGS.
>               (cpu_flags): Add CpuTSXLDTRK.
>               * i386-opc.h (enum): Add CpuTSXLDTRK.
>               (i386_cpu_flags): Add cputsxldtrk.
>               * i386-opc.tbl: Add XSUSPLDTRK insns.
>               * i386-init.h: Regenerate.
>               * i386-tbl.h: Likewise.

Please do

1. Rebase against the current master.
2. Remove blank line at the end of testsuite/gas/i386/tsxldtrk.s to fix

$ git am 0001-Add-support-for-intel-TSXLDTRK-instructions.patch
Applying: Add support for intel TSXLDTRK instructions
.git/rebase-apply/patch:108: new blank line at EOF.
+
warning: 1 line adds whitespace errors.

3. Add x86-64-tsxldtrk.d.

--
H.J.
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RE: Add support for Intel TSXLDTRK instructions

Sourceware - binutils list mailing list


> -----Original Message-----
> From: H.J. Lu <[hidden email]>
> Sent: Thursday, April 2, 2020 8:57 PM
> To: Cui, Lili <[hidden email]>
> Cc: [hidden email]; Zhang, Annita <[hidden email]>; Liu,
> Hongtao <[hidden email]>; Lu, Hongjiu <[hidden email]>; Xiao,
> Wei3 <[hidden email]>
> Subject: Re: Add support for Intel TSXLDTRK instructions
>
> On Wed, Apr 1, 2020 at 8:20 PM Cui, Lili via Binutils
> <[hidden email]> wrote:
> >
> > Hi all,
> >
> > This patch is about to enable binutils support for TSXLDTRK which
> > would
> >
> > be in GLC. There's only 2 instructions: XRESLDTRK, XSUSLDTRK, more
> >
> > details please refer to
> >
> > https://software.intel.com/sites/default/files/managed/c5/15/architect
> > ure-instruction-set-extensions-programming-reference.pdf
> >
> >
> >
> > Make check-gas is ok.
> >
> >
> > gas/ChangeLog:
> >
> >               2020-04-02  Lili Cui  <[hidden email]>
> >               * config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
> >               (cpu_noarch): Likewise.
> >               * doc/c-i386.texi: Document TSXLDTRK.
> >               * testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
> >               * testsuite/gas/i386/tsxldtrk.d: Likewise.
> >               * testsuite/gas/i386/tsxldtrk.s: Likewise.
> >
> > opcodes/gas/ChangeLog:
> >
> >               2020-04-02  Lili Cui  <[hidden email]>
> >               * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
> >               (prefix_table): New instructions (see prefixes above).
> >               (rm_table): Likewise
> >               * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
> >               CPU_ANY_TSXLDTRK_FLAGS.
> >               (cpu_flags): Add CpuTSXLDTRK.
> >               * i386-opc.h (enum): Add CpuTSXLDTRK.
> >               (i386_cpu_flags): Add cputsxldtrk.
> >               * i386-opc.tbl: Add XSUSPLDTRK insns.
> >               * i386-init.h: Regenerate.
> >               * i386-tbl.h: Likewise.
>
> Please do
>
> 1. Rebase against the current master.
> 2. Remove blank line at the end of testsuite/gas/i386/tsxldtrk.s to fix
>
> $ git am 0001-Add-support-for-intel-TSXLDTRK-instructions.patch
> Applying: Add support for intel TSXLDTRK instructions
> .git/rebase-apply/patch:108: new blank line at EOF.
> +
> warning: 1 line adds whitespace errors.
>
> 3. Add x86-64-tsxldtrk.d.
>
> --
> H.J.

Done, Thanks.

Lili.

0001-Add-support-for-intel-TSXLDTRK-instructions.patch (12K) Download Attachment
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Re: Add support for Intel TSXLDTRK instructions

Sourceware - binutils list mailing list
On Thu, Apr 2, 2020 at 8:30 PM Cui, Lili <[hidden email]> wrote:

>
>
>
> > -----Original Message-----
> > From: H.J. Lu <[hidden email]>
> > Sent: Thursday, April 2, 2020 8:57 PM
> > To: Cui, Lili <[hidden email]>
> > Cc: [hidden email]; Zhang, Annita <[hidden email]>; Liu,
> > Hongtao <[hidden email]>; Lu, Hongjiu <[hidden email]>; Xiao,
> > Wei3 <[hidden email]>
> > Subject: Re: Add support for Intel TSXLDTRK instructions
> >
> > On Wed, Apr 1, 2020 at 8:20 PM Cui, Lili via Binutils
> > <[hidden email]> wrote:
> > >
> > > Hi all,
> > >
> > > This patch is about to enable binutils support for TSXLDTRK which
> > > would
> > >
> > > be in GLC. There's only 2 instructions: XRESLDTRK, XSUSLDTRK, more
> > >
> > > details please refer to
> > >
> > > https://software.intel.com/sites/default/files/managed/c5/15/architect
> > > ure-instruction-set-extensions-programming-reference.pdf
> > >
> > >
> > >
> > > Make check-gas is ok.
> > >
> > >
> > > gas/ChangeLog:
> > >
> > >               2020-04-02  Lili Cui  <[hidden email]>
> > >               * config/tc-i386.c (cpu_arch): Add .TSXLDTRK.
> > >               (cpu_noarch): Likewise.
> > >               * doc/c-i386.texi: Document TSXLDTRK.
> > >               * testsuite/gas/i386/i386.exp: Run TSXLDTRK tests.
> > >               * testsuite/gas/i386/tsxldtrk.d: Likewise.
> > >               * testsuite/gas/i386/tsxldtrk.s: Likewise.
> > >
> > > opcodes/gas/ChangeLog:
> > >
> > >               2020-04-02  Lili Cui  <[hidden email]>
> > >               * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
> > >               (prefix_table): New instructions (see prefixes above).
> > >               (rm_table): Likewise
> > >               * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
> > >               CPU_ANY_TSXLDTRK_FLAGS.
> > >               (cpu_flags): Add CpuTSXLDTRK.
> > >               * i386-opc.h (enum): Add CpuTSXLDTRK.
> > >               (i386_cpu_flags): Add cputsxldtrk.
> > >               * i386-opc.tbl: Add XSUSPLDTRK insns.
> > >               * i386-init.h: Regenerate.
> > >               * i386-tbl.h: Likewise.
> >
> > Please do
> >
> > 1. Rebase against the current master.
> > 2. Remove blank line at the end of testsuite/gas/i386/tsxldtrk.s to fix
> >
> > $ git am 0001-Add-support-for-intel-TSXLDTRK-instructions.patch
> > Applying: Add support for intel TSXLDTRK instructions
> > .git/rebase-apply/patch:108: new blank line at EOF.
> > +
> > warning: 1 line adds whitespace errors.
> >
> > 3. Add x86-64-tsxldtrk.d.
> >
> > --
> > H.J.
>
>
> Done, Thanks.
>
> Lili.

@@ -962,6 +962,7 @@ enum
   PREFIX_0F01_REG_3_RM_1,
   PREFIX_0F01_REG_5_MOD_0,
   PREFIX_0F01_REG_5_MOD_3_RM_0,
+  PREFIX_0F01_REG_5_MOD_3_RM_1,
   PREFIX_0F01_REG_5_MOD_3_RM_2,
   PREFIX_0F01_REG_7_MOD_3_RM_2,
   PREFIX_0F01_REG_7_MOD_3_RM_3,
@@ -3646,6 +3647,16 @@ static const struct dis386 prefix_table[][4] = {
   {
     { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
     { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
+    { Bad_Opcode },
+    { "xsuspldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
+  },
+
+  /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
      ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^  Typo.  Should be
PREFIX_0F01_REG_5_MOD_3_RM_1
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
   },

   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */

OK with that fix.

Thanks.

--
H.J.