[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.

classic Classic list List threaded Threaded
28 messages Options
12
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.

Matthew Wahab-2
Hello,

ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch set adds the 16-bit
Adv.SIMD vector and scalar instructions to binutils, making them
available when both +simd and +fp16 architecture extensions are enabled.
The series also adds support for a new vector type, 2H, used by the FP16
scalar pairwise instructions.

The patches in this series:
- Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding
   routines.
- Add FP16 instructions in the group Vector Three Register Same.
- Add FP16 instructions in the group Scalar Three Register Same.
- Add FP16 instructions in the group Vector Two Register Misc.
- Add FP16 instructions in the group Scalar Two Register Misc.
- Add FP16 instructions in the group Vector Indexed Element.
- Add FP16 instructions in the group Scalar Indexed Element.
- Add FP16 instructions in the group Adv.SIMD Across Lanes.
- Add FP16 instructions in the group Adv.SIMD Modified Immediate.
- Rework some code for handling vector types to weaken its assumptions
   about available vector-types.
- Add support for the 2H vector type.
- Add FP16 instructions in the group Adv.SIMD Scalar Pairwise.
- Add FP16 instructions in the group Adv.SIMD Shift By Immediate.
- Add a FP16 instructions in the group Adv.SIMD Scalar Shift By
   Immediate.

This patch adds the feature macro SIMD_F16 to the AArch64
encoding/decoding routines. It is used to decide when the new
instructions are available to the assembler and is true when both +simd
and +fp16 are selected.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-tbl.h (aarch64_feature_simd_f16): New.
        (SIMD_F16): New.

0001-AArch64-Add-FP16-SIMD-feature-flag.patch (1K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.

Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Three Register Same, making them
available when +simd+fp16 is enabled.

The instructions added are: FMAXNM, FMAXNMP, FNMINNM, FMINNMP, FMLA,
FMLS, FADD, FADDP, FSUB, FABD, FMULX, FMUL, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FMAX, FMAXP, FMIN, FMINP, FRECPS, FDIV and FRSQRTS.

The general form for these instructions is
   <OP> <Vd>.<T>, <Vs>.<T>, <Vm>.<T>
   where T is 4h or 8h.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: New.
        * gas/aarch64/advsimd-fp16.s: New.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_V3SAMEH): New.
        (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
        fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
        fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
        fcmgt, facgt and fminp to the vector three same group.


0002-AArch64-Add-FP16-Vector-three-same-instructions-I.patch (16K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Three Register Same, making them
available when +simd+fp16 is enabled.

The instructions added are: FABD, FMULX, FCMEQ, FCMGE, FCMGT, FACGE,
FACGT, FRECPS and FRSQRTS.

The general form for these instructions is
   <OP> <Hd>, <Hs>, <Hm>

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for scalar three register same
        instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
        fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
        facgt to the scalar three same group.


0003-AArch64-Add-FP16-Scalar-three-same-instructions-II.patch (6K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Two Register Misc, making them
available when +simd+fp16 is enabled.

The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FABS,
FNEG, FRINTN, FRINTA, FRINTP, FRINTM, FRINTX, FRINTZ, FRINTI, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FSQRT.

The general form for these instructions is
   <OP> <Vd>.<T>, <Vs>.<T>
   where T is 4h or 8h.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for vector two register misc.
        instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_V2SAMEH): New.
        (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
        fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
        frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
        fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
        and fsqrt to the vector register misc. group.


0004-AArch64-Add-FP16-vector-two-register-misc.-instructi.patch (17K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Two Register Misc, making them
available when +simd+fp16 is enabled.

The instructions added are: FCMGT, FCMGE, FCMEQ, FCMLE, FCMLT, FCVTNS,
FCVTNU, FCVTPS, FCVTPU, FCVTMS, FCVTMU, FCVTZS, FCVTZU, FCVTAS, FCVTAU,
SCVTF, UCVTF, FRECPE, FRSQRTE and FRECPX.

The general form for these instructions is
   <OP> <Hd>, <Hs>
or
   <OP> <Hd>, <Hs>, #0.0

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for scalar two register misc.
        instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
        (QL_S_2SAMEH): New.
        (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
        fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
        frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
        fcvtzu and frsqrte to the scalar two register misc. group.


0005-AArch64-Add-FP16-Scalar-two-register-misc.-instructi.patch (10K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Vector Indexed Element, making them available
when +simd+fp16 is enabled.

The instructions added are: FMLA, FMLS, FMUL and FMULX.

The general form for these instructions is
   <OP> <V>.<T>, <V>.<T>, <V>.h[<idx>]
   where T is 4h or 8h

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
        instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
        (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
        fmulx to the vector indexed element group.


0006-AArch64-Add-FP16-Vector-indexed-element-instructions.patch (5K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.

The instructions added are: FMLA, FMLS, FMUL and FMULX.

The general form for these instructions is
   <OP> <Hd>, <Hs>, <V>.h[<idx>]

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
        instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
        fmls, fmul and fmulx to the scalar indexed element group.


0007-AArch64-Add-FP16-Scalar-indexed-element-instructions.patch (3K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 8/14] Support FP16 Adv.SIMD Across Lanes instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Across Lanes, making them available
when +simd+fp16 is enabled.

The instructions added are: FMAXNMV, FMAXV, FMINNMV and FMINV.

The general form for these instructions is
    <OP> <Hd>, <V>.<T>
    where T is 4h or 8h.

The new instructions valid make uses of the 8H and 4H that were
previously illegal. The patch adjusts a test for illegal uses of vector
types to take this into account.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
        instructions.
         * gas/aarch64/illegal.d: Update expected output.
         * gas/aarch64/illegal.s: Replace test for illegal use of 'h'
        specifier.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_XLANES_FP_H): New.
        (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
        fminnmv, fminv to the Adv.SIMD across lanes group.


0008-AArch64-Add-FP16-Adv.SIMD-across-lanes-instructions-.patch (5K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.

The instruction added is: FMOV.

The form of this instructions is
     <OP> <Hd>, #<imm>

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
        instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_SIMD_IMM_H): New.
        (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
        modified immediate group.


0009-AArch64-Add-FP16-Adv.SIMD-modified-immediate-instruc.patch (3K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 10/14] Rework code mapping vector types to operand qualifiers.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type. This patch reworks
code in the assembler to allow the addition of the new type.

The new vector type requires the addtion of a new operand qualifier to
the enum aarch64_opnd_qualifier which is defined
include/opcodes/aarch64.h, in the group prefixed by AARCH64_OPN_QLF_V_.

The correctness of the GAS utility function
tc-aarch64.c:vectype_to_qualifier is heavily dependent on the number and
ordering of this group. In particular, it makes assumptions about the
positions of the members of the group that are not true if a qualifier
for type 2H is added before the qualifier for 4H.

This patch reworks the function to weaken its assumptions, making it
calculate positions in the group from the type (B, H, S, D, Q) and
register width.

Tested for aarch64-none-linux-gnu with cross-compiled check-binutils and
check-gas.

Ok for trunk?
Matthew

gas/
2015-12-10  Matthew Wahab  <[hidden email]>

        * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
        qualifier from per-type base and offet.



0010-AArch64-GAS-Rework-code-mapping-vector-types-to-binu.patch (2K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 11/14] Add support for the 2H vector type.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.

The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interfers with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.

Tested for aarch64-none-linux-gnu with cross-compiled check-binutils and
check-gas.

Ok for trunk?
Matthew

gas/
2015-12-10  Matthew Wahab  <[hidden email]>

        * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
        take into account new vector type 2H.
        (vectype_to_qualifier): Likewise.

include/opcode/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64.h (enum aarch64_opnd_qualifier): Add
        AARCH64_OPND_QLF_V_2H.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
        and adjust calculation to ignore qualifier for type 2H.
        * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".



0011-AArch64-Add-support-for-2H-vector-type.patch (4K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.

The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP

The general form for these instructions is
    <OP> <Hd>, <V>.<T>
    where T is 4h or 8h.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
        Pairwise instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_XLANES_FP_H): New.
        (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
        fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.


0012-AArch64-Add-FP16-Adv.SIMD-Scalar-Pairwise-instructio.patch (4K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 13/14] Support FP16 Adv.SIMD Shift By Immediate instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Shift By Immediate to support FP16,
making this support available when +simd+fp16 is enabled.

The new instructions legal make some uses of the 4h vector type that had
been invalid. This patch adjusts a test that checks for these uses.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
    <OP> <Vd>.<T>, <Vs>.<T>, #<imm>
    where T is 4h or 8h.

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD across lanes
        instructions.
         * gas/aarch64/illegal.d: Update expected output.
         * gas/aarch64/illegal.s: Replace tests for illegal use of 'h'
        specifier.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_VSHIFT_H): New.
        (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
        and fcvtzu to the Adv.SIMD shift by immediate group.


0013-AArch64-Add-FP16-Adv.SIMD-shift-by-immediate-instruc.patch (6K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

[AArch64][PATCH 14/14] Support FP16 Adv.SIMD Scalar Shift By Immediate instructions.

Matthew Wahab-2
In reply to this post by Matthew Wahab-2
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch extends
instructions in the group Adv.SIMD Scalar Shift By Immediate to support
FP16, making this support available when +simd+fp16 is enabled.

The extended instructions are: SCVTF, FCVTZS, UCVTF and FCVTZU.

The general form for these instructions is
    <OP> <Hd>, <Hs>, #<imm>

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <[hidden email]>

        * gas/aarch64/advsimd-fp16.d: Update expected output.
        * gas/aarch64/advsimd-fp16: Add tests for Adv.SIMD scalar shift
        by immediate instructions.

opcodes/
2015-12-10  Matthew Wahab  <[hidden email]>

        * aarch64-asm-2.c: Regenerate.
        * aarch64-dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.
        * aarch64-tbl.h (QL_SSHIFT_H): New.
        (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
        and fcvtzu to the Adv.SIMD scalar shift by immediate group.


0014-AArch64-Add-FP16-Adv.SIMD-scalar-shift-by-immediate-.patch (4K) Download Attachment
Reply | Threaded
Open this post in threaded view
|

Re: [AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.

Marcus
In reply to this post by Matthew Wahab-2
On 11 December 2015 at 11:48, Matthew Wahab <[hidden email]> wrote:

> opcodes/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * aarch64-tbl.h (aarch64_feature_simd_f16): New.
>         (SIMD_F16): New.

OK /Marcus
Reply | Threaded
Open this post in threaded view
|

Re: [AArch64][PATCH 2/14] Support ARMv8.2 FP16 Vector Three Same instructions.

Marcus
In reply to this post by Matthew Wahab-2
On 11 December 2015 at 11:58, Matthew Wahab <[hidden email]> wrote:

> gas/testsuite/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * gas/aarch64/advsimd-fp16.d: New.
>         * gas/aarch64/advsimd-fp16.s: New.
>
> opcodes/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * aarch64-asm-2.c: Regenerate.
>         * aarch64-dis-2.c: Regenerate.
>         * aarch64-opc-2.c: Regenerate.
>         * aarch64-tbl.h (QL_V3SAMEH): New.
>         (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
>         fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
>         fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
>         fcmgt, facgt and fminp to the vector three same group.
>

OK /Marcus
Reply | Threaded
Open this post in threaded view
|

Re: [AArch64][PATCH 3/14] Support ARMv8.2 FP16 Scalar Three Same instructions.

Marcus
In reply to this post by Matthew Wahab-2
On 11 December 2015 at 12:01, Matthew Wahab <[hidden email]> wrote:

> gas/testsuite/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * gas/aarch64/advsimd-fp16.d: Update expected output.
>         * gas/aarch64/advsimd-fp16.s: Add tests for scalar three register
> same
>         instructions.
>
> opcodes/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * aarch64-asm-2.c: Regenerate.
>         * aarch64-dis-2.c: Regenerate.
>         * aarch64-opc-2.c: Regenerate.
>         * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
>         fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and
>         facgt to the scalar three same group.
>

OK /Marcus
Reply | Threaded
Open this post in threaded view
|

Re: [AArch64][PATCH 4/14] Support FP16 Vector Two Register Misc. instructions.

Marcus
In reply to this post by Matthew Wahab-2
On 11 December 2015 at 12:03, Matthew Wahab <[hidden email]> wrote:

> gas/testsuite/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * gas/aarch64/advsimd-fp16.d: Update expected output.
>         * gas/aarch64/advsimd-fp16.s: Add tests for vector two register
> misc.
>         instructions.
>
> opcodes/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * aarch64-asm-2.c: Regenerate.
>         * aarch64-dis-2.c: Regenerate.
>         * aarch64-opc-2.c: Regenerate.
>         * aarch64-tbl.h (QL_V2SAMEH): New.
>         (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
>         fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
>         frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
>         fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
>         and fsqrt to the vector register misc. group.
>

OK /Marcus
Reply | Threaded
Open this post in threaded view
|

Re: [AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.

Marcus
In reply to this post by Matthew Wahab-2
On 11 December 2015 at 12:05, Matthew Wahab <[hidden email]> wrote:

> gas/testsuite/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * gas/aarch64/advsimd-fp16.d: Update expected output.
>         * gas/aarch64/advsimd-fp16.s: Add tests for scalar two register
> misc.
>         instructions.
>
> opcodes/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * aarch64-asm-2.c: Regenerate.
>         * aarch64-dis-2.c: Regenerate.
>         * aarch64-opc-2.c: Regenerate.
>         * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
>         (QL_S_2SAMEH): New.
>         (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
>         fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
>         frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
>         fcvtzu and frsqrte to the scalar two register misc. group.
>

OK /Marcus
Reply | Threaded
Open this post in threaded view
|

Re: [AArch64][PATCH 6/14] Support FP16 Vector Indexed Element instructions.

Marcus
In reply to this post by Matthew Wahab-2
On 11 December 2015 at 12:07, Matthew Wahab <[hidden email]> wrote:

> gas/testsuite/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * gas/aarch64/advsimd-fp16.d: Update expected output.
>         * gas/aarch64/advsimd-fp16.s: Add tests for vector indexed element
>         instructions.
>
> opcodes/
> 2015-12-10  Matthew Wahab  <[hidden email]>
>
>         * aarch64-asm-2.c: Regenerate.
>         * aarch64-dis-2.c: Regenerate.
>         * aarch64-opc-2.c: Regenerate.
>         * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
>         (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
>         fmulx to the vector indexed element group.
>

OK /Marcus
12